URL
https://opencores.org/ocsvn/rtcclock/rtcclock/trunk
[/] [rtcclock/] [trunk/] [rtl/] [rtclight.v] - Diff between revs 8 and 10
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| Rev 8 |
Rev 10 |
| Line 70... |
Line 70... |
assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
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assign tm_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b001));
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assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
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assign sw_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b010));
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assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
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assign al_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b011));
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assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
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assign sp_sel = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_addr[2:0]==3'b100));
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reg [39:0] ck_counter;
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reg ck_carry;
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reg ck_carry;
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reg [39:0] ck_counter;
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initial ck_carry = 1'b0;
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initial ck_counter = 40'h00;
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always @(posedge i_clk)
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always @(posedge i_clk)
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{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
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{ ck_carry, ck_counter } <= ck_counter + { 8'h00, ckspeed };
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wire ck_pps;
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wire ck_pps;
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reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
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reg ck_prepps, ck_ppm, ck_pph, ck_ppd;
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