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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [RTF65002PIC.v] - Diff between revs 10 and 13
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Rev 13 |
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// |Supported Cycles: SLAVE,READ/WRITE
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// |Supported Cycles: SLAVE,READ/WRITE
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// | SLAVE,BLOCK READ/WRITE
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// | SLAVE,BLOCK READ/WRITE
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// | SLAVE,RMW
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// | SLAVE,RMW
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// |Data port, size: 16 bit
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// |Data port, size: 32 bit
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// |Data port, granularity: 16 bit
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// |Data port, granularity: 32 bit
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// |Data port, maximum operand size: 16 bit
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// |Data port, maximum operand size: 32 bit
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// |Data transfer ordering: Undefined
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// |Data transfer ordering: Undefined
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// |Data transfer sequencing: Undefined
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// |Data transfer sequencing: Undefined
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// |Clock frequency constraints: none
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// |Clock frequency constraints: none
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