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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013,2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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// Datapath calculations - eight bit mode
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// Datapath calculations - eight/sixteen bit mode
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// ============================================================================
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// ============================================================================
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//
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//
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BYTE_CALC:
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BYTE_CALC:
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begin
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begin
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state <= BYTE_IFETCH;
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state <= BYTE_IFETCH;
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wadr <= radr;
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wadr2LSB <= radr2LSB;
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store_what <= `STW_DEF8;
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store_what <= `STW_DEF8;
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case(ir[7:0])
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case(ir[7:0])
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`ADC_IMM,`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I: begin res8 <= acc8 + b8 + {7'b0,cf}; end
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`ADC_IMM,`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_IYL,`ADC_I,`ADC_IL,`ADC_AL,`ADC_ALX,`ADC_DSP,`ADC_DSPIY: begin res8 <= acc8 + b8 + {7'b0,cf}; end
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`SBC_IMM,`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I: begin res8 <= acc8 - b8 - {7'b0,~cf}; end
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`SBC_IMM,`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_IYL,`SBC_I,`SBC_IL,`SBC_AL,`SBC_ALX,`SBC_DSP,`SBC_DSPIY: begin res8 <= acc8 - b8 - {7'b0,~cf}; end
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`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I: begin res8 <= acc8 - b8; end
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`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_IYL,`CMP_I,`CMP_IL,`CMP_AL,`CMP_ALX,`CMP_DSP,`CMP_DSPIY: begin res8 <= acc8 - b8; end
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`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I: begin res8 <= acc8 & b8; end
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`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_IYL,`AND_I,`AND_IL,`AND_AL,`AND_ALX,`AND_DSP,`AND_DSPIY: begin res8 <= acc8 & b8; end
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`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_I: begin res8 <= acc8 | b8; end
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`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_IYL,`ORA_I,`ORA_IL,`ORA_AL,`ORA_ALX,`ORA_DSP,`ORA_DSPIY: begin res8 <= acc8 | b8; end
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`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_I: begin res8 <= acc8 ^ b8; end
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`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_IYL,`EOR_I,`EOR_IL,`EOR_AL,`EOR_ALX,`EOR_DSP,`EOR_DSPIY: begin res8 <= acc8 ^ b8; end
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`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_I: begin res8 <= b8; end
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`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_IYL,`LDA_I,`LDA_IL,`LDA_AL,`LDA_ALX,`LDA_DSP,`LDA_DSPIY: begin res8 <= b8; end
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`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX: begin res8 <= acc8 & b8; end
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`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX: begin res8 <= acc8 & b8; end
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`TRB_ZP,`TRB_ABS: begin res8 <= ~acc8 & b8; wdat <= {4{~acc8 & b8}}; state <= STORE1; end
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`TSB_ZP,`TSB_ABS: begin res8 <= acc8 | b8; wdat <= {4{acc8 | b8}}; state <= STORE1; end
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`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin res8 <= b8; end
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`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin res8 <= b8; end
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`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin res8 <= b8; end
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`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin res8 <= b8; end
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`CPX_IMM,`CPX_ZP,`CPX_ABS: begin res8 <= x8 - b8; end
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`CPX_IMM,`CPX_ZP,`CPX_ABS: begin res8 <= x8 - b8; end
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`CPY_IMM,`CPY_ZP,`CPY_ABS: begin res8 <= y8 - b8; end
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`CPY_IMM,`CPY_ZP,`CPY_ABS: begin res8 <= y8 - b8; end
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`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin res8 <= {b8,1'b0}; wdat <= {4{b8[6:0],1'b0}}; state <= STORE1; end
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`TRB_ZP,`TRB_ABS: begin res8 <= ~acc8 & b8; wdat <= ~acc8 & b8; state <= STORE1; end
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`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin res8 <= {b8,cf}; wdat <= {4{b8[6:0],cf}}; state <= STORE1; end
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`TSB_ZP,`TSB_ABS: begin res8 <= acc8 | b8; wdat <= acc8 | b8; state <= STORE1; end
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`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin res8 <= {b8[0],1'b0,b8[7:1]}; wdat <= {4{1'b0,b8[7:1]}}; state <= STORE1; end
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`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin res8 <= {b8,1'b0}; wdat <= {b8[6:0],1'b0}; state <= STORE1; end
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`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin res8 <= {b8[0],cf,b8[7:1]}; wdat <= {4{cf,b8[7:1]}}; state <= STORE1; end
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`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin res8 <= {b8,cf}; wdat <= {b8[6:0],cf}; state <= STORE1; end
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`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX: begin res8 <= b8 + 8'd1; wdat <= {4{b8+8'd1}}; state <= STORE1; end
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`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin res8 <= {b8[0],1'b0,b8[7:1]}; wdat <= {1'b0,b8[7:1]}; state <= STORE1; end
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`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin res8 <= b8 - 8'd1; wdat <= {4{b8-8'd1}}; state <= STORE1; end
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`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin res8 <= {b8[0],cf,b8[7:1]}; wdat <= {cf,b8[7:1]}; state <= STORE1; end
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`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX: begin res8 <= b8 + 8'd1; wdat <= {b8+8'd1}; state <= STORE1; end
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`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin res8 <= b8 - 8'd1; wdat <= {b8-8'd1}; state <= STORE1; end
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endcase
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endcase
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end
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end
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No newline at end of file
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No newline at end of file
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