URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_calc.v] - Diff between revs 32 and 35

Rev 32	Rev 35
Line 24...	Line 24...
`BYTE_CALC:`	`BYTE_CALC:`
`begin`	`begin`
`state <= BYTE_IFETCH;`	`state <= BYTE_IFETCH;`
`wadr <= radr;`	`wadr <= radr;`
`wadr2LSB <= radr2LSB;`	`wadr2LSB <= radr2LSB;`
store_what <= `STW_DEF;	store_what <= `STW_DEF8;
`case(ir[7:0])`	`case(ir[7:0])`
`ADC_IMM,`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I: begin res8 <= acc8 + b8 + {7'b0,cf}; end	`ADC_IMM,`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I: begin res8 <= acc8 + b8 + {7'b0,cf}; end
`SBC_IMM,`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I: begin res8 <= acc8 - b8 - {7'b0,~cf}; end	`SBC_IMM,`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I: begin res8 <= acc8 - b8 - {7'b0,~cf}; end
`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I: begin res8 <= acc8 - b8; end	`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I: begin res8 <= acc8 - b8; end
`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I: begin res8 <= acc8 & b8; end	`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I: begin res8 <= acc8 & b8; end