| Line 101... |
Line 101... |
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
res8 <= y8 - ir[15:8];
|
res8 <= y8 - ir[15:8];
|
end
|
end
|
// Handle zp mode
|
// Handle zp mode
|
`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,`LDA_ZP,
|
`LDX_ZP,`LDY_ZP,`LDA_ZP:
|
`LDX_ZP,`LDY_ZP,`BIT_ZP,`CPX_ZP,`CPY_ZP,
|
begin
|
|
pc <= pc + 32'd2;
|
|
radr <= zp_address[31:2];
|
|
radr2LSB <= zp_address[1:0];
|
|
load_what <= `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
|
|
`BIT_ZP,`CPX_ZP,`CPY_ZP,
|
`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
|
`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
radr <= zp_address[31:2];
|
radr <= zp_address[31:2];
|
radr2LSB <= zp_address[1:0];
|
radr2LSB <= zp_address[1:0];
|
state <= LOAD1;
|
load_what <= `BYTE_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ZP:
|
`STA_ZP:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
wadr <= zp_address[31:2];
|
wadr <= zp_address[31:2];
|
| Line 143... |
Line 152... |
wadr2LSB <= zp_address[1:0];
|
wadr2LSB <= zp_address[1:0];
|
wdat <= {4{8'h00}};
|
wdat <= {4{8'h00}};
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
// Handle zp,x mode
|
// Handle zp,x mode
|
`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,`LDA_ZPX,
|
`LDY_ZPX,`LDA_ZPX:
|
`LDY_ZPX,`BIT_ZPX,
|
begin
|
|
pc <= pc + 32'd2;
|
|
radr <= zpx_address[31:2];
|
|
radr2LSB <= zpx_address[1:0];
|
|
load_what <= `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
|
|
`BIT_ZPX,
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
radr <= zpx_address[31:2];
|
radr <= zpx_address[31:2];
|
radr2LSB <= zpx_address[1:0];
|
radr2LSB <= zpx_address[1:0];
|
state <= LOAD1;
|
load_what <= `BYTE_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ZPX:
|
`STA_ZPX:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
wadr <= zpx_address[31:2];
|
wadr <= zpx_address[31:2];
|
| Line 182... |
Line 200... |
`LDX_ZPY:
|
`LDX_ZPY:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
radr <= zpy_address[31:2];
|
radr <= zpy_address[31:2];
|
radr2LSB <= zpy_address[1:0];
|
radr2LSB <= zpy_address[1:0];
|
state <= LOAD1;
|
load_what <= `BYTE_71;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`STX_ZPY:
|
`STX_ZPY:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
wadr <= zpy_address[31:2];
|
wadr <= zpy_address[31:2];
|
| Line 198... |
Line 217... |
`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
|
`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
radr <= zpx_address[31:2];
|
radr <= zpx_address[31:2];
|
radr2LSB <= zpx_address[1:0];
|
radr2LSB <= zpx_address[1:0];
|
state <= BYTE_IX1;
|
load_what <= `IA_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
// Handle (zp),y
|
// Handle (zp),y
|
`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
|
`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
radr <= zp_address[31:2];
|
radr <= zp_address[31:2];
|
radr2LSB <= zp_address[1:0];
|
radr2LSB <= zp_address[1:0];
|
state <= BYTE_IY1;
|
isIY <= `TRUE;
|
|
load_what <= `IA_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
// Handle abs
|
// Handle abs
|
`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,`LDA_ABS,
|
`LDA_ABS,`LDX_ABS,`LDY_ABS:
|
|
begin
|
|
pc <= pc + 32'd3;
|
|
radr <= abs_address[31:2];
|
|
radr2LSB <= abs_address[1:0];
|
|
load_what <= `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
|
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
|
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
|
`LDX_ABS,`LDY_ABS,
|
|
`CPX_ABS,`CPY_ABS,
|
`CPX_ABS,`CPY_ABS,
|
`BIT_ABS:
|
`BIT_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
radr <= abs_address[31:2];
|
radr <= abs_address[31:2];
|
radr2LSB <= abs_address[1:0];
|
radr2LSB <= abs_address[1:0];
|
state <= LOAD1;
|
load_what <= `BYTE_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ABS:
|
`STA_ABS:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
wadr <= abs_address[31:2];
|
wadr <= abs_address[31:2];
|
| Line 260... |
Line 290... |
`LDY_ABSX:
|
`LDY_ABSX:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
radr <= absx_address[31:2];
|
radr <= absx_address[31:2];
|
radr2LSB <= absx_address[1:0];
|
radr2LSB <= absx_address[1:0];
|
state <= LOAD1;
|
load_what <= `BYTE_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ABSX:
|
`STA_ABSX:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
wadr <= absx_address[31:2];
|
wadr <= absx_address[31:2];
|
| Line 285... |
Line 316... |
`LDX_ABSY:
|
`LDX_ABSY:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
radr <= absy_address[31:2];
|
radr <= absy_address[31:2];
|
radr2LSB <= absy_address[1:0];
|
radr2LSB <= absy_address[1:0];
|
state <= LOAD1;
|
load_what <= `BYTE_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ABSY:
|
`STA_ABSY:
|
begin
|
begin
|
pc <= pc + 32'd3;
|
pc <= pc + 32'd3;
|
wadr <= absy_address[31:2];
|
wadr <= absy_address[31:2];
|
| Line 301... |
Line 333... |
`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
|
`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
|
begin
|
begin
|
pc <= pc + 32'd2;
|
pc <= pc + 32'd2;
|
radr <= zp_address[31:2];
|
radr <= zp_address[31:2];
|
radr2LSB <= zp_address[1:0];
|
radr2LSB <= zp_address[1:0];
|
state <= BYTE_IX1;
|
load_what <= `IA_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`BRK:
|
`BRK:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
radr2LSB <= sp[1:0];
|
radr2LSB <= sp[1:0];
|
| Line 338... |
Line 371... |
end
|
end
|
`JMP_IND:
|
`JMP_IND:
|
begin
|
begin
|
radr <= abs_address[31:2];
|
radr <= abs_address[31:2];
|
radr2LSB <= abs_address[1:0];
|
radr2LSB <= abs_address[1:0];
|
state <= BYTE_JMP_IND1;
|
load_what <= `PC_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`JMP_INDX:
|
`JMP_INDX:
|
begin
|
begin
|
radr <= absx_address[31:2];
|
radr <= absx_address[31:2];
|
radr2LSB <= absx_address[1:0];
|
radr2LSB <= absx_address[1:0];
|
state <= BYTE_JMP_IND1;
|
load_what <= `PC_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`JSR:
|
`JSR:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
radr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
wadr <= {spage[31:8],sp[7:2]};
|
| Line 414... |
Line 449... |
`RTS,`RTL:
|
`RTS,`RTL:
|
begin
|
begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
state <= BYTE_RTS1;
|
load_what <= `PC_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`RTI: begin
|
`RTI: begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
state <= BYTE_RTI9;
|
load_what <= `SR_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
|
begin
|
begin
|
// if (ir[15:8]==8'hFE) begin
|
// if (ir[15:8]==8'hFE) begin
|
// radr <= {24'h1,sp[7:2]};
|
// radr <= {24'h1,sp[7:2]};
|
| Line 547... |
Line 584... |
`PLP:
|
`PLP:
|
begin
|
begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
state <= BYTE_PLP1;
|
load_what <= `SR_70;
|
|
state <= LOAD_MAC1;
|
pc <= pc + 32'd1;
|
pc <= pc + 32'd1;
|
end
|
end
|
`PLA,`PLX,`PLY:
|
`PLA,`PLX,`PLY:
|
begin
|
begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr <= {spage[31:8],sp_inc[7:2]};
|
radr2LSB <= sp_inc[1:0];
|
radr2LSB <= sp_inc[1:0];
|
sp <= sp_inc;
|
sp <= sp_inc;
|
state <= PLA1;
|
load_what <= `BYTE_71;
|
|
state <= LOAD_MAC1;
|
pc <= pc + 32'd1;
|
pc <= pc + 32'd1;
|
end
|
end
|
default: // unimplemented opcode
|
default: // unimplemented opcode
|
pc <= pc + 32'd1;
|
pc <= pc + 32'd1;
|
endcase
|
endcase
|
