OpenCores
URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_decode.v] - Diff between revs 21 and 25

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 21 Rev 25
Line 342... Line 342... 
                        begin
 
                        begin
 
                                radr <= {spage[31:8],sp[7:2]};
 
                                radr <= {spage[31:8],sp[7:2]};
 
                                radr2LSB <= sp[1:0];
 
                                radr2LSB <= sp[1:0];
 
                                wadr <= {spage[31:8],sp[7:2]};
 
                                wadr <= {spage[31:8],sp[7:2]};
 
                                wadr2LSB <= sp[1:0];
 
                                wadr2LSB <= sp[1:0];
 
                                wdat <= {4{pcp1[31:24]}};
 
                                wdat <= {4{pcp2[31:24]}};
 
                                cyc_o <= 1'b1;
 
                                cyc_o <= 1'b1;
 
                                stb_o <= 1'b1;
 
                                stb_o <= 1'b1;
 
                                we_o <= 1'b1;
 
                                we_o <= 1'b1;
 
                                case(sp[1:0])
 
                                case(sp[1:0])
 
                                2'd0:   sel_o <= 4'b0001;
 
                                2'd0:   sel_o <= 4'b0001;
 
                                2'd1:   sel_o <= 4'b0010;
 
                                2'd1:   sel_o <= 4'b0010;
 
                                2'd2:   sel_o <= 4'b0100;
 
                                2'd2:   sel_o <= 4'b0100;
 
                                2'd3:   sel_o <= 4'b1000;
 
                                2'd3:   sel_o <= 4'b1000;
 
                                endcase
 
                                endcase
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                dat_o <= {4{pcp1[31:24]}};
 
                                dat_o <= {4{pcp2[31:24]}};
 
                                sp <= sp_dec;
 
                                sp <= sp_dec;
 
                                vect <= `BYTE_IRQ_VECT;
 
                                vect <= `BYTE_IRQ_VECT;
 
                                state <= BYTE_IRQ1;
 
                                state <= BYTE_IRQ1;
 
                                bf <= 1'b1;
 
                                bf <= 1'b1;
 
                        end
 
                        end
Line 514... Line 514... 
                                endcase
 
                                endcase
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                dat_o <= {4{sr8}};
 
                                dat_o <= {4{sr8}};
 
                                wdat <= {4{sr8}};
 
                                wdat <= {4{sr8}};
 
                                sp <= sp_dec;
 
                                sp <= sp_dec;
 
                                state <= PHP1;
 
                                state <= STORE2;
 
 
 
                                pc <= pc + 32'd1;
 
                        end
 
                        end
 
                `PHA:
 
                `PHA:
 
                        begin
 
                        begin
 
                                cyc_o <= 1'b1;
 
                                cyc_o <= 1'b1;
 
                                stb_o <= 1'b1;
 
                                stb_o <= 1'b1;
Line 535... Line 536... 
                                endcase
 
                                endcase
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                dat_o <= {4{acc8}};
 
                                dat_o <= {4{acc8}};
 
                                wdat <= {4{acc8}};
 
                                wdat <= {4{acc8}};
 
                                sp <= sp_dec;
 
                                sp <= sp_dec;
 
                                state <= PHP1;
 
                                state <= STORE2;
 
 
 
                                pc <= pc + 32'd1;
 
                        end
 
                        end
 
                `PHX:
 
                `PHX:
 
                        begin
 
                        begin
 
                                cyc_o <= 1'b1;
 
                                cyc_o <= 1'b1;
 
                                stb_o <= 1'b1;
 
                                stb_o <= 1'b1;
Line 556... Line 558... 
                                endcase
 
                                endcase
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                dat_o <= {4{x8}};
 
                                dat_o <= {4{x8}};
 
                                wdat <= {4{x8}};
 
                                wdat <= {4{x8}};
 
                                sp <= sp_dec;
 
                                sp <= sp_dec;
 
                                state <= PHP1;
 
                                state <= STORE2;
 
 
 
                                pc <= pc + 32'd1;
 
                        end
 
                        end
 
                `PHY:
 
                `PHY:
 
                        begin
 
                        begin
 
                                cyc_o <= 1'b1;
 
                                cyc_o <= 1'b1;
 
                                stb_o <= 1'b1;
 
                                stb_o <= 1'b1;
Line 577... Line 580... 
                                endcase
 
                                endcase
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                                dat_o <= {4{y8}};
 
                                dat_o <= {4{y8}};
 
                                wdat <= {4{y8}};
 
                                wdat <= {4{y8}};
 
                                sp <= sp_dec;
 
                                sp <= sp_dec;
 
                                state <= PHP1;
 
                                pc <= pc + 32'd1;
 
 
 
                                state <= STORE2;
 
                        end
 
                        end
 
                `PLP:
 
                `PLP:
 
                        begin
 
                        begin
 
                                radr <= {spage[31:8],sp_inc[7:2]};
 
                                radr <= {spage[31:8],sp_inc[7:2]};
 
                                radr2LSB <= sp_inc[1:0];
 
                                radr2LSB <= sp_inc[1:0];

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.