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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013,2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// ============================================================================
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// ============================================================================
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//
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//
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BYTE_DECODE:
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BYTE_DECODE:
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begin
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begin
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first_ifetch <= `TRUE;
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first_ifetch <= `TRUE;
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state <= BYTE_IFETCH;
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next_state(BYTE_IFETCH);
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pc <= pc + pc_inc8;
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pc <= pc + pc_inc8;
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case(ir[7:0])
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case(ir[7:0])
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`SEP: ; // see byte_ifetch
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`REP: ;
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// XBA cannot be done in the ifetch stage because it'd repeat when there
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// was a cache miss, causing the instruction to be done twice.
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`XBA:
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begin
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res16 <= {acc[7:0],acc[15:8]};
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res8 <= acc[15:8]; // for flag settings
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end
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`STP: begin clk_en <= 1'b0; end
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`STP: begin clk_en <= 1'b0; end
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`NAT: begin em <= 1'b0; state <= IFETCH; end
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// `NAT: begin em <= 1'b0; state <= IFETCH; end
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`NOP: ;
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`WDM: if (ir[15:8]==`XCE) begin
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em <= 1'b0;
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next_state(IFETCH);
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pc <= pc + 32'd2;
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end
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// Switching the processor mode always zeros out the upper part of the index registers.
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// switching to 816 mode sets 8 bit memory/indexes
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`XCE: begin
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m816 <= ~cf;
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cf <= ~m816;
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if (~cf) begin
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m_bit <= 1'b1;
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x_bit <= 1'b1;
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end
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x[31:8] <= 24'd0;
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y[31:8] <= 24'd0;
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end
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// `NOP: ; // may help routing
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`CLC: begin cf <= 1'b0; end
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`CLC: begin cf <= 1'b0; end
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`SEC: begin cf <= 1'b1; end
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`SEC: begin cf <= 1'b1; end
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`CLV: begin vf <= 1'b0; end
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`CLV: begin vf <= 1'b0; end
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`CLI: begin im <= 1'b0; end
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`CLI: begin im <= 1'b0; end
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`SEI: begin im <= 1'b1; end
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`SEI: begin im <= 1'b1; end
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`CLD: begin df <= 1'b0; end
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`CLD: begin df <= 1'b0; end
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`SED: begin df <= 1'b1; end
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`SED: begin df <= 1'b1; end
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`WAI: begin wai <= 1'b1; end
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`WAI: begin wai <= 1'b1; end
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`DEX: begin res8 <= x[7:0] - 8'd1; end
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`DEX: begin res8 <= x_dec[7:0]; res16 <= x_dec[15:0]; end
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`INX: begin res8 <= x[7:0] + 8'd1; end
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`INX: begin res8 <= x_inc[7:0]; res16 <= x_inc[15:0]; end
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`DEY: begin res8 <= y[7:0] - 8'd1; end
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`DEY: begin res8 <= y_dec[7:0]; res16 <= y_dec[15:0]; end
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`INY: begin res8 <= y[7:0] + 8'd1; end
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`INY: begin res8 <= y_inc[7:0]; res16 <= y_inc[15:0]; end
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`DEA: begin res8 <= acc[7:0] - 8'd1; end
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`DEA: begin res8 <= acc_dec[7:0]; res16 <= acc_dec[15:0]; end
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`INA: begin res8 <= acc[7:0] + 8'd1; end
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`INA: begin res8 <= acc_inc[7:0]; res16 <= acc_inc[15:0]; end
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`TSX,`TSA: begin res8 <= sp[7:0]; end
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`TSX,`TSA: begin res8 <= sp[7:0]; res16 <= sp[15:0]; end
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`TXS,`TXA,`TXY: begin res8 <= x[7:0]; end
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`TXS,`TXA,`TXY: begin res8 <= x[7:0]; res16 <= xb16 ? x[15:0] : {8'h00,x8}; end
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`TAX,`TAY,`TAS: begin res8 <= acc[7:0]; end
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`TAX,`TAY: begin res8 <= acc[7:0]; res16 <= m16 ? acc[15:0] : {8'h00,acc8}; end
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`TYA,`TYX: begin res8 <= y[7:0]; end
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`TAS: begin res8 <= acc[7:0]; res16 <= acc[15:0]; end
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`ASL_ACC: begin res8 <= {acc8,1'b0}; end
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`TYA,`TYX: begin res8 <= y[7:0]; res16 <= xb16 ? y[15:0] : {8'h00,y8}; end
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`ROL_ACC: begin res8 <= {acc8,cf}; end
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`TDC: begin res16 <= dpr; end
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`LSR_ACC: begin res8 <= {acc8[0],1'b0,acc8[7:1]}; end
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`TCD: begin res16 <= acc[15:0]; end
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`ROR_ACC: begin res8 <= {acc8[0],cf,acc8[7:1]}; end
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`ASL_ACC: begin res8 <= {acc8,1'b0}; res16 <= {acc16,1'b0}; end
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`ROL_ACC: begin res8 <= {acc8,cf}; res16 <= {acc16,cf}; end
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`LSR_ACC: begin res8 <= {acc8[0],1'b0,acc8[7:1]}; res16 <= {acc16[0],1'b0,acc16[15:1]}; end
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`ROR_ACC: begin res8 <= {acc8[0],cf,acc8[7:1]}; res16 <= {acc16[0],cf,acc16[15:1]}; end
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// Handle # mode
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// Handle # mode
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`LDA_IMM,`LDX_IMM,`LDY_IMM:
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`LDA_IMM:
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begin
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res8 <= ir[15:8];
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res16 <= ir[23:8];
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end
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`LDX_IMM,`LDY_IMM:
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begin
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begin
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pc <= pc + 32'd2;
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res8 <= ir[15:8];
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res8 <= ir[15:8];
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res16 <= ir[23:8];
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end
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end
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`ADC_IMM:
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`ADC_IMM:
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begin
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begin
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res8 <= acc8 + ir[15:8] + {7'b0,cf};
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res8 <= acc8 + ir[15:8] + {7'b0,cf};
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res16 <= acc16 + ir[23:8] + {15'b0,cf};
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b8 <= ir[15:8]; // for overflow calc
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b8 <= ir[15:8]; // for overflow calc
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b16 <= ir[23:8];
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end
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end
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`SBC_IMM:
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`SBC_IMM:
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begin
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begin
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// res8 <= acc8 - ir[15:8] - ~cf;
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// res8 <= acc8 - ir[15:8] - ~cf;
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res8 <= acc8 - ir[15:8] - {7'b0,~cf};
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res8 <= acc8 - ir[15:8] - {7'b0,~cf};
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res16 <= acc16 - ir[23:8] - {15'b0,~cf};
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$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
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$display("sbc: %h= %h-%h-%h", acc8 - ir[15:8] - {7'b0,~cf},acc8,ir[15:8],~cf);
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b8 <= ir[15:8]; // for overflow calc
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b8 <= ir[15:8]; // for overflow calc
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b16 <= ir[23:8];
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end
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end
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`AND_IMM,`BIT_IMM:
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`AND_IMM,`BIT_IMM:
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begin
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begin
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res8 <= acc8 & ir[15:8];
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res8 <= acc8 & ir[15:8];
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res16 <= acc16 & ir[23:8];
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b8 <= ir[15:8]; // for bit flags
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b8 <= ir[15:8]; // for bit flags
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b16 <= ir[23:8];
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end
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end
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`ORA_IMM: res8 <= acc8 | ir[15:8];
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`ORA_IMM: begin res8 <= acc8 | ir[15:8]; res16 <= acc16 | ir[23:8]; end
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`EOR_IMM: res8 <= acc8 ^ ir[15:8];
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`EOR_IMM: begin res8 <= acc8 ^ ir[15:8]; res16 <= acc16 ^ ir[23:8]; end
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`CMP_IMM: res8 <= acc8 - ir[15:8];
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`CMP_IMM: begin res8 <= acc8 - ir[15:8]; res16 <= acc16 - ir[23:8]; end
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`CPX_IMM: res8 <= x8 - ir[15:8];
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`CPX_IMM: begin res8 <= x8 - ir[15:8]; res16 <= x16 - ir[23:8]; end
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`CPY_IMM: res8 <= y8 - ir[15:8];
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`CPY_IMM: begin res8 <= y8 - ir[15:8]; res16 <= y16 - ir[23:8]; end
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// Handle zp mode
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// Handle zp mode
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`LDX_ZP,`LDY_ZP,`LDA_ZP:
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`LDA_ZP:
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begin
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begin
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radr <= zp_address[31:2];
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radr <= zp_address[31:2];
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radr2LSB <= zp_address[1:0];
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radr2LSB <= zp_address[1:0];
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load_what <= `BYTE_71;
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load_what <= m16 ? `HALF_71 : `BYTE_71;
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state <= LOAD_MAC1;
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end
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`LDX_ZP,`LDY_ZP:
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begin
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radr <= zp_address[31:2];
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radr2LSB <= zp_address[1:0];
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load_what <= xb16 ? `HALF_71 : `BYTE_71;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
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`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
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`ADC_ZP,`SBC_ZP,`AND_ZP,`ORA_ZP,`EOR_ZP,`CMP_ZP,
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`BIT_ZP,`CPX_ZP,`CPY_ZP,
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`BIT_ZP,
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`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
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`ASL_ZP,`ROL_ZP,`LSR_ZP,`ROR_ZP,`INC_ZP,`DEC_ZP,`TRB_ZP,`TSB_ZP:
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begin
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begin
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radr <= zp_address[31:2];
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radr <= zp_address[31:2];
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radr2LSB <= zp_address[1:0];
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radr2LSB <= zp_address[1:0];
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load_what <= `BYTE_70;
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wadr <= zp_address[31:2];
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wadr2LSB <= zp_address[1:0];
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load_what <= m16 ? `HALF_70 : `BYTE_70;
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state <= LOAD_MAC1;
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end
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`CPX_ZP,`CPY_ZP:
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begin
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radr <= zp_address[31:2];
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radr2LSB <= zp_address[1:0];
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load_what <= xb16 ? `HALF_70 : `BYTE_70;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
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`STA_ZP:
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`STA_ZP:
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begin
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begin
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wadr <= zp_address[31:2];
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wadr <= zp_address[31:2];
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wadr2LSB <= zp_address[1:0];
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wadr2LSB <= zp_address[1:0];
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store_what <= `STW_ACC8;
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store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
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state <= STORE1;
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state <= STORE1;
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end
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end
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`STX_ZP:
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`STX_ZP:
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begin
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begin
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wadr <= zp_address[31:2];
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wadr <= zp_address[31:2];
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wadr2LSB <= zp_address[1:0];
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wadr2LSB <= zp_address[1:0];
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store_what <= `STW_X8;
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store_what <= xb16 ? `STW_X70 : `STW_X8;
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state <= STORE1;
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state <= STORE1;
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end
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end
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`STY_ZP:
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`STY_ZP:
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begin
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begin
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wadr <= zp_address[31:2];
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wadr <= zp_address[31:2];
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wadr2LSB <= zp_address[1:0];
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wadr2LSB <= zp_address[1:0];
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store_what <= `STW_Y8;
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store_what <= xb16 ? `STW_Y70 : `STW_Y8;
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state <= STORE1;
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state <= STORE1;
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end
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end
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`STZ_ZP:
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`STZ_ZP:
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begin
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begin
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wadr <= zp_address[31:2];
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wadr <= zp_address[31:2];
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wadr2LSB <= zp_address[1:0];
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wadr2LSB <= zp_address[1:0];
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store_what <= `STW_Z8;
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store_what <= m16 ? `STW_Z70 : `STW_Z8;
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state <= STORE1;
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state <= STORE1;
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end
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end
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// Handle zp,x mode
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// Handle zp,x mode
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`LDY_ZPX,`LDA_ZPX:
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`LDA_ZPX:
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begin
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begin
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radr <= zpx_address[31:2];
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radr <= zpx_address[31:2];
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radr2LSB <= zpx_address[1:0];
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radr2LSB <= zpx_address[1:0];
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load_what <= `BYTE_71;
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load_what <= m16 ? `HALF_71 : `BYTE_71;
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state <= LOAD_MAC1;
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end
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`LDY_ZPX:
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begin
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radr <= zpx_address[31:2];
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radr2LSB <= zpx_address[1:0];
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load_what <= xb16 ? `HALF_71 : `BYTE_71;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
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`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
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`ADC_ZPX,`SBC_ZPX,`AND_ZPX,`ORA_ZPX,`EOR_ZPX,`CMP_ZPX,
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`BIT_ZPX,
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`BIT_ZPX,
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`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
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`ASL_ZPX,`ROL_ZPX,`LSR_ZPX,`ROR_ZPX,`INC_ZPX,`DEC_ZPX:
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begin
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begin
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radr <= zpx_address[31:2];
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radr <= zpx_address[31:2];
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radr2LSB <= zpx_address[1:0];
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radr2LSB <= zpx_address[1:0];
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load_what <= `BYTE_70;
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wadr <= zpx_address[31:2];
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wadr2LSB <= zpx_address[1:0];
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load_what <= m16 ? `HALF_70 : `BYTE_70;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
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`STA_ZPX:
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`STA_ZPX:
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begin
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begin
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wadr <= zpx_address[31:2];
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wadr <= zpx_address[31:2];
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wadr2LSB <= zpx_address[1:0];
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wadr2LSB <= zpx_address[1:0];
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store_what <= `STW_ACC8;
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store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
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state <= STORE1;
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state <= STORE1;
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end
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end
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`STY_ZPX:
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`STY_ZPX:
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begin
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begin
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wadr <= zpx_address[31:2];
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wadr <= zpx_address[31:2];
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wadr2LSB <= zpx_address[1:0];
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wadr2LSB <= zpx_address[1:0];
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store_what <= `STW_Y8;
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store_what <= xb16 ? `STW_Y70 : `STW_Y8;
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state <= STORE1;
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state <= STORE1;
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end
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end
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`STZ_ZPX:
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`STZ_ZPX:
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begin
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begin
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wadr <= zpx_address[31:2];
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wadr <= zpx_address[31:2];
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wadr2LSB <= zpx_address[1:0];
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wadr2LSB <= zpx_address[1:0];
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store_what <= `STW_Z8;
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store_what <= m16 ? `STW_Z70 : `STW_Z8;
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state <= STORE1;
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state <= STORE1;
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end
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end
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// Handle zp,y
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// Handle zp,y
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`LDX_ZPY:
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`LDX_ZPY:
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begin
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begin
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radr <= zpy_address[31:2];
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radr <= zpy_address[31:2];
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radr2LSB <= zpy_address[1:0];
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radr2LSB <= zpy_address[1:0];
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load_what <= `BYTE_71;
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load_what <= xb16 ? `HALF_71 : `BYTE_71;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
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`STX_ZPY:
|
`STX_ZPY:
|
begin
|
begin
|
wadr <= zpy_address[31:2];
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wadr <= zpy_address[31:2];
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wadr2LSB <= zpy_address[1:0];
|
wadr2LSB <= zpy_address[1:0];
|
store_what <= `STW_X8;
|
store_what <= xb16 ? `STW_X70 : `STW_X8;
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state <= STORE1;
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state <= STORE1;
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end
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end
|
// Handle (zp,x)
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// Handle (zp,x)
|
`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
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`ADC_IX,`SBC_IX,`AND_IX,`ORA_IX,`EOR_IX,`CMP_IX,`LDA_IX,`STA_IX:
|
begin
|
begin
|
radr <= zpx_address[31:2];
|
radr <= zpx_address[31:2];
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radr2LSB <= zpx_address[1:0];
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radr2LSB <= zpx_address[1:0];
|
load_what <= `IA_70;
|
load_what <= `IA_70;
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store_what <= `STW_ACC8;
|
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
// Handle (zp),y
|
// Handle (zp),y
|
`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
|
`ADC_IY,`SBC_IY,`AND_IY,`ORA_IY,`EOR_IY,`CMP_IY,`LDA_IY,`STA_IY:
|
begin
|
begin
|
radr <= zp_address[31:2];
|
radr <= zp_address[31:2];
|
radr2LSB <= zp_address[1:0];
|
radr2LSB <= zp_address[1:0];
|
isIY <= `TRUE;
|
isIY <= `TRUE;
|
load_what <= `IA_70;
|
load_what <= `IA_70;
|
store_what <= `STW_ACC8;
|
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
// Handle abs
|
// Handle abs
|
`LDA_ABS,`LDX_ABS,`LDY_ABS:
|
`LDA_ABS:
|
begin
|
begin
|
radr <= abs_address[31:2];
|
radr <= abs_address[31:2];
|
radr2LSB <= abs_address[1:0];
|
radr2LSB <= abs_address[1:0];
|
load_what <= `BYTE_71;
|
load_what <= m16 ? `HALF_71 : `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`LDX_ABS,`LDY_ABS:
|
|
begin
|
|
radr <= abs_address[31:2];
|
|
radr2LSB <= abs_address[1:0];
|
|
load_what <= xb16 ? `HALF_71 : `BYTE_71;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
|
`ADC_ABS,`SBC_ABS,`AND_ABS,`ORA_ABS,`EOR_ABS,`CMP_ABS,
|
`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
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`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`TRB_ABS,`TSB_ABS,
|
`CPX_ABS,`CPY_ABS,
|
|
`BIT_ABS:
|
`BIT_ABS:
|
begin
|
begin
|
radr <= abs_address[31:2];
|
radr <= abs_address[31:2];
|
radr2LSB <= abs_address[1:0];
|
radr2LSB <= abs_address[1:0];
|
load_what <= `BYTE_70;
|
wadr <= abs_address[31:2];
|
|
wadr2LSB <= abs_address[1:0];
|
|
load_what <= m16 ? `HALF_70 : `BYTE_70;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`CPX_ABS,`CPY_ABS:
|
|
begin
|
|
radr <= abs_address[31:2];
|
|
radr2LSB <= abs_address[1:0];
|
|
load_what <= xb16 ? `HALF_70 : `BYTE_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ABS:
|
`STA_ABS:
|
begin
|
begin
|
wadr <= abs_address[31:2];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= abs_address[1:0];
|
wadr2LSB <= abs_address[1:0];
|
store_what <= `STW_ACC8;
|
store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STX_ABS:
|
`STX_ABS:
|
begin
|
begin
|
wadr <= abs_address[31:2];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= abs_address[1:0];
|
wadr2LSB <= abs_address[1:0];
|
store_what <= `STW_X8;
|
store_what <= xb16 ? `STW_X70 : `STW_X8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STY_ABS:
|
`STY_ABS:
|
begin
|
begin
|
wadr <= abs_address[31:2];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= abs_address[1:0];
|
wadr2LSB <= abs_address[1:0];
|
store_what <= `STW_Y8;
|
store_what <= xb16 ? `STW_Y70 : `STW_Y8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STZ_ABS:
|
`STZ_ABS:
|
begin
|
begin
|
wadr <= abs_address[31:2];
|
wadr <= abs_address[31:2];
|
wadr2LSB <= abs_address[1:0];
|
wadr2LSB <= abs_address[1:0];
|
store_what <= `STW_Z8;
|
store_what <= m16 ? `STW_Z70 : `STW_Z8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
// Handle abs,x
|
// Handle abs,x
|
`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,`LDA_ABSX,
|
`LDA_ABSX:
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX,
|
begin
|
|
radr <= absx_address[31:2];
|
|
radr2LSB <= absx_address[1:0];
|
|
load_what <= m16 ? `HALF_71 : `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADC_ABSX,`SBC_ABSX,`AND_ABSX,`ORA_ABSX,`EOR_ABSX,`CMP_ABSX,
|
|
`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`BIT_ABSX:
|
|
begin
|
|
radr <= absx_address[31:2];
|
|
radr2LSB <= absx_address[1:0];
|
|
wadr <= absx_address[31:2];
|
|
wadr2LSB <= absx_address[1:0];
|
|
load_what <= m16 ? `HALF_70 : `BYTE_70;
|
|
state <= LOAD_MAC1;
|
|
end
|
`LDY_ABSX:
|
`LDY_ABSX:
|
begin
|
begin
|
radr <= absx_address[31:2];
|
radr <= absx_address[31:2];
|
radr2LSB <= absx_address[1:0];
|
radr2LSB <= absx_address[1:0];
|
load_what <= `BYTE_70;
|
load_what <= xb16 ? `HALF_71 : `BYTE_71;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ABSX:
|
`STA_ABSX:
|
begin
|
begin
|
wadr <= absx_address[31:2];
|
wadr <= absx_address[31:2];
|
wadr2LSB <= absx_address[1:0];
|
wadr2LSB <= absx_address[1:0];
|
store_what <= `STW_ACC8;
|
store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`STZ_ABSX:
|
`STZ_ABSX:
|
begin
|
begin
|
wadr <= absx_address[31:2];
|
wadr <= absx_address[31:2];
|
wadr2LSB <= absx_address[1:0];
|
wadr2LSB <= absx_address[1:0];
|
store_what <= `STW_Z8;
|
store_what <= m16 ? `STW_Z70 : `STW_Z8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
// Handle abs,y
|
// Handle abs,y
|
`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY,`LDA_ABSY,
|
`LDA_ABSY:
|
|
begin
|
|
radr <= absy_address[31:2];
|
|
radr2LSB <= absy_address[1:0];
|
|
load_what <= m16 ? `HALF_71 : `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADC_ABSY,`SBC_ABSY,`AND_ABSY,`ORA_ABSY,`EOR_ABSY,`CMP_ABSY:
|
|
begin
|
|
radr <= absy_address[31:2];
|
|
radr2LSB <= absy_address[1:0];
|
|
load_what <= m16 ? `HALF_70 : `BYTE_70;
|
|
state <= LOAD_MAC1;
|
|
end
|
`LDX_ABSY:
|
`LDX_ABSY:
|
begin
|
begin
|
radr <= absy_address[31:2];
|
radr <= absy_address[31:2];
|
radr2LSB <= absy_address[1:0];
|
radr2LSB <= absy_address[1:0];
|
load_what <= `BYTE_70;
|
load_what <= xb16 ? `HALF_71 : `BYTE_71;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STA_ABSY:
|
`STA_ABSY:
|
begin
|
begin
|
wadr <= absy_address[31:2];
|
wadr <= absy_address[31:2];
|
wadr2LSB <= absy_address[1:0];
|
wadr2LSB <= absy_address[1:0];
|
store_what <= `STW_ACC8;
|
store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
|
`ifdef SUPPORT_816
|
|
// Handle d,sp
|
|
`LDA_DSP:
|
|
begin
|
|
radr <= dsp_address[31:2];
|
|
radr2LSB <= dsp_address[1:0];
|
|
load_what <= m16 ? `HALF_71 : `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADC_DSP,`SBC_DSP,`CMP_DSP,`ORA_DSP,`AND_DSP,`EOR_DSP:
|
|
begin
|
|
radr <= dsp_address[31:2];
|
|
radr2LSB <= dsp_address[1:0];
|
|
load_what <= m16 ? `HALF_70 : `BYTE_70;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`STA_DSP:
|
|
begin
|
|
wadr <= dsp_address[31:2];
|
|
wadr2LSB <= dsp_address[1:0];
|
|
store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
|
|
state <= STORE1;
|
|
end
|
|
// Handle (d,sp),y
|
|
`ADC_DSPIY,`SBC_DSPIY,`CMP_DSPIY,`ORA_DSPIY,`AND_DSPIY,`EOR_DSPIY,`LDA_DSPIY,`STA_DSPIY:
|
|
begin
|
|
radr <= dsp_address[31:2];
|
|
radr2LSB <= dsp_address[1:0];
|
|
isIY <= `TRUE;
|
|
load_what <= `IA_70;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
// Handle [zp],y
|
|
`ADC_IYL,`SBC_IYL,`AND_IYL,`ORA_IYL,`EOR_IYL,`CMP_IYL,`LDA_IYL,`STA_IYL:
|
|
begin
|
|
radr <= zp_address[31:2];
|
|
radr2LSB <= zp_address[1:0];
|
|
isIY24 <= `TRUE;
|
|
load_what <= `IA_70;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
// Handle al
|
|
`LDA_AL:
|
|
begin
|
|
radr <= al_address[31:2];
|
|
radr2LSB <= al_address[1:0];
|
|
load_what <= m16 ? `HALF_71 : `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADC_AL,`SBC_AL,`AND_AL,`ORA_AL,`EOR_AL,`CMP_AL:
|
|
begin
|
|
radr <= al_address[31:2];
|
|
radr2LSB <= al_address[1:0];
|
|
load_what <= m16 ? `HALF_70 : `BYTE_70;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`STA_AL:
|
|
begin
|
|
wadr <= al_address[31:2];
|
|
wadr2LSB <= al_address[1:0];
|
|
store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
|
|
state <= STORE1;
|
|
end
|
|
// Handle alx
|
|
`LDA_ALX:
|
|
begin
|
|
radr <= alx_address[31:2];
|
|
radr2LSB <= alx_address[1:0];
|
|
load_what <= m16 ? `HALF_71 : `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ADC_ALX,`SBC_ALX,`AND_ALX,`ORA_ALX,`EOR_ALX,`CMP_ALX:
|
|
begin
|
|
radr <= alx_address[31:2];
|
|
radr2LSB <= alx_address[1:0];
|
|
load_what <= m16 ? `HALF_70 : `BYTE_70;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`STA_ALX:
|
|
begin
|
|
wadr <= alx_address[31:2];
|
|
wadr2LSB <= alx_address[1:0];
|
|
store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
|
|
state <= STORE1;
|
|
end
|
|
// Handle [zp]
|
|
`ADC_IL,`SBC_IL,`AND_IL,`ORA_IL,`EOR_IL,`CMP_IL,`LDA_IL,`STA_IL:
|
|
begin
|
|
isI24 <= `TRUE;
|
|
radr <= zp_address[31:2];
|
|
radr2LSB <= zp_address[1:0];
|
|
load_what <= `IA_70;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`endif
|
// Handle (zp)
|
// Handle (zp)
|
`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I:
|
`ADC_I,`SBC_I,`AND_I,`ORA_I,`EOR_I,`CMP_I,`LDA_I,`STA_I,`PEI:
|
begin
|
begin
|
radr <= zp_address[31:2];
|
radr <= zp_address[31:2];
|
radr2LSB <= zp_address[1:0];
|
radr2LSB <= zp_address[1:0];
|
load_what <= `IA_70;
|
load_what <= `IA_70;
|
store_what <= `STW_ACC8;
|
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BRK:
|
`BRK:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
set_sp();
|
radr2LSB <= sp[1:0];
|
store_what <= m816 ? `STW_PC2316 : `STW_PC158;// `STW_PC3124;
|
wadr <= {spage[31:8],sp[7:2]};
|
|
wadr2LSB <= sp[1:0];
|
|
sp <= sp_dec;
|
|
store_what <= `STW_PC3124;
|
|
state <= STORE1;
|
state <= STORE1;
|
bf <= !hwi;
|
bf <= !hwi;
|
end
|
end
|
|
`ifdef SUPPORT_816
|
|
`COP:
|
|
begin
|
|
set_sp();
|
|
store_what <= m816 ? `STW_PC2316 : `STW_PC158;// `STW_PC3124;
|
|
state <= STORE1;
|
|
vect <= `COP_VECT_816;
|
|
end
|
|
`endif
|
`JMP:
|
`JMP:
|
begin
|
begin
|
pc[15:0] <= abs_address[15:0];
|
pc[15:0] <= ir[23:8];
|
end
|
end
|
`JML:
|
`JML:
|
begin
|
begin
|
pc <= ir[39:8];
|
pc[23:0] <= ir[31:8];
|
end
|
end
|
`JMP_IND:
|
`JMP_IND:
|
begin
|
begin
|
radr <= abs_address[31:2];
|
radr <= abs_address[31:2];
|
radr2LSB <= abs_address[1:0];
|
radr2LSB <= abs_address[1:0];
|
| Line 323... |
Line 528... |
radr <= absx_address[31:2];
|
radr <= absx_address[31:2];
|
radr2LSB <= absx_address[1:0];
|
radr2LSB <= absx_address[1:0];
|
load_what <= `PC_70;
|
load_what <= `PC_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`JSR:
|
`JSR,`JSR_INDX:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
set_sp();
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
store_what <= `STW_PC158;
|
store_what <= `STW_PC158;
|
sp <= sp_dec;
|
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`JSL:
|
`JSL:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
set_sp();
|
wadr <= {spage[31:8],sp[7:2]};
|
store_what <= `STW_PC2316;
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
store_what <= `STW_PC3124;
|
|
sp <= sp_dec;
|
|
state <= STORE1;
|
|
end
|
|
`JSR_INDX:
|
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr2LSB <= sp[1:0];
|
|
sp <= sp_dec;
|
|
store_what <= `STW_PC158;
|
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`RTS,`RTL:
|
`RTS,`RTL:
|
begin
|
begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
inc_sp();
|
radr2LSB <= sp_inc[1:0];
|
|
sp <= sp_inc;
|
|
load_what <= `PC_70;
|
load_what <= `PC_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`RTI: begin
|
`RTI: begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
inc_sp();
|
radr2LSB <= sp_inc[1:0];
|
|
sp <= sp_inc;
|
|
load_what <= `SR_70;
|
load_what <= `SR_70;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
|
`BEQ,`BNE,`BPL,`BMI,`BCC,`BCS,`BVC,`BVS,`BRA:
|
|
/*
|
|
begin
|
|
if (ir[15:8]==8'hFF) begin
|
|
if (takb)
|
|
pc <= pc + {{16{ir[31]}},ir[31:16]};
|
|
else
|
|
pc <= pc + 32'd4;
|
|
end
|
|
else */
|
begin
|
begin
|
if (ir[15:8]==8'hFF) begin
|
|
if (takb)
|
if (takb)
|
pc <= pc + {{16{ir[31]}},ir[31:16]};
|
pc <= pc + pc_inc8 + {{24{ir[15]}},ir[15:8]};
|
else
|
else
|
pc <= pc + 32'd4;
|
pc <= pc + pc_inc8;
|
end
|
end
|
else
|
//end
|
|
`BRL: pc <= pc + pc_inc8 + {{16{ir[23]}},ir[23:8]};
|
|
`PHP:
|
begin
|
begin
|
if (takb)
|
set_sp();
|
pc <= pc + {{24{ir[15]}},ir[15:8]} + 32'd2;
|
store_what <= `STW_SR70;
|
else
|
state <= STORE1;
|
pc <= pc + 32'd2;
|
|
end
|
end
|
|
`PHA: tsk_push(`STW_ACC8,`STW_ACC70,m16);
|
|
`PHX: tsk_push(`STW_X8,`STW_X70,xb16);
|
|
`PHY: tsk_push(`STW_Y8,`STW_Y70,xb16);
|
|
`PLP:
|
|
begin
|
|
inc_sp();
|
|
load_what <= `SR_70;
|
|
state <= LOAD_MAC1;
|
end
|
end
|
`PHP:
|
`PLA:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
inc_sp();
|
radr2LSB <= sp[1:0];
|
load_what <= m16 ? `HALF_71S : `BYTE_71;
|
wadr <= {spage[31:8],sp[7:2]};
|
state <= LOAD_MAC1;
|
wadr2LSB <= sp[1:0];
|
end
|
sp <= sp_dec;
|
`PLX,`PLY:
|
store_what <= `STW_SR70;
|
begin
|
|
inc_sp();
|
|
load_what <= xb16 ? `HALF_71S : `BYTE_71;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`ifdef SUPPORT_816
|
|
`PHB:
|
|
begin
|
|
set_sp();
|
|
store_what <= `STW_DBR;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`PHA:
|
`PHD:
|
begin
|
begin
|
radr <= {spage[31:8],sp[7:2]};
|
set_sp();
|
radr2LSB <= sp[1:0];
|
store_what <= `STW_DPR158;
|
wadr <= {spage[31:8],sp[7:2]};
|
|
wadr2LSB <= sp[1:0];
|
|
store_what <= `STW_ACC8;
|
|
sp <= sp_dec;
|
|
state <= STORE1;
|
|
end
|
|
`PHX:
|
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
wadr2LSB <= sp[1:0];
|
|
store_what <= `STW_X8;
|
|
sp <= sp_dec;
|
|
state <= STORE1;
|
|
end
|
|
`PHY:
|
|
begin
|
|
radr <= {spage[31:8],sp[7:2]};
|
|
radr2LSB <= sp[1:0];
|
|
wadr <= {spage[31:8],sp[7:2]};
|
|
wadr2LSB <= sp[1:0];
|
|
store_what <= `STW_Y8;
|
|
sp <= sp_dec;
|
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`PLP:
|
`PHK:
|
begin
|
begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
set_sp();
|
radr2LSB <= sp_inc[1:0];
|
store_what <= `STW_PC2316;
|
sp <= sp_inc;
|
state <= STORE1;
|
load_what <= `SR_70;
|
end
|
state <= LOAD_MAC1;
|
`PEA:
|
|
begin
|
|
tmp16 <= ir[23:8];
|
|
set_sp();
|
|
store_what <= `STW_TMP158;
|
|
state <= STORE1;
|
end
|
end
|
`PLA,`PLX,`PLY:
|
`PER:
|
begin
|
begin
|
radr <= {spage[31:8],sp_inc[7:2]};
|
tmp16 <= pc[15:0] + ir[23:8] + 16'd3;
|
radr2LSB <= sp_inc[1:0];
|
set_sp();
|
sp <= sp_inc;
|
store_what <= `STW_TMP158;
|
|
state <= STORE1;
|
|
end
|
|
`PLB:
|
|
begin
|
|
inc_sp();
|
load_what <= `BYTE_71;
|
load_what <= `BYTE_71;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
`PLD:
|
|
begin
|
|
inc_sp();
|
|
load_what <= `HALF_71S;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`MVN,`MVP:
|
|
begin
|
|
radr <= mvnsrc_address[31:2];
|
|
radr2LSB <= mvnsrc_address[1:0];
|
|
load_what <= `BYTE_72;
|
|
pc <= pc; // override increment above
|
|
state <= LOAD_MAC1;
|
|
end
|
|
`endif
|
default: // unimplemented opcode
|
default: // unimplemented opcode
|
pc <= pc + 32'd1;
|
pc <= pc + 32'd1;
|
endcase
|
endcase
|
end
|
end
|
|
|
No newline at end of file
|
No newline at end of file
|
