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// IRQ processing states
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// ============================================================================
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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// IRQ processing states for 65C02 emulation mode
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// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.
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// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.
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//
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//
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BYTE_IRQ1:
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BYTE_IRQ1:
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if (ack_i) begin
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if (ack_i) begin
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state <= BYTE_IRQ2;
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retstate <= BYTE_IRQ2;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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sel_o <= 4'h0;
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sp <= sp_dec;
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sp <= sp_dec;
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if (dhit) begin
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if (dhit) begin
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wrsel <= sel_o;
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wrsel <= sel_o;
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wr <= 1'b1;
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wr <= 1'b1;
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end
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end
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state <= BYTE_IRQ2;
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else if (write_allocate) begin
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state <= WAIT_DHIT;
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dmiss <= `TRUE;
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end
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end
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end
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BYTE_IRQ2:
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BYTE_IRQ2:
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begin
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begin
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radr <= {24'h1,sp[7:2]};
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radr <= {24'h1,sp[7:2]};
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radr2LSB <= sp[1:0];
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radr2LSB <= sp[1:0];
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Line 61... |
dat_o <= {4{pc[23:16]}};
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dat_o <= {4{pc[23:16]}};
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state <= BYTE_IRQ3;
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state <= BYTE_IRQ3;
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end
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end
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BYTE_IRQ3:
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BYTE_IRQ3:
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if (ack_i) begin
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if (ack_i) begin
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state <= BYTE_IRQ4;
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retstate <= BYTE_IRQ4;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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sel_o <= 4'h0;
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sp <= sp_dec;
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sp <= sp_dec;
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if (dhit) begin
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if (dhit) begin
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wrsel <= sel_o;
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wrsel <= sel_o;
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wr <= 1'b1;
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wr <= 1'b1;
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end
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end
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state <= BYTE_IRQ4;
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else if (write_allocate) begin
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state <= WAIT_DHIT;
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dmiss <= `TRUE;
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end
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end
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end
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BYTE_IRQ4:
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BYTE_IRQ4:
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begin
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begin
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radr <= {24'h1,sp[7:2]};
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radr <= {24'h1,sp[7:2]};
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radr2LSB <= sp[1:0];
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radr2LSB <= sp[1:0];
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Line 99... |
dat_o <= {4{pc[15:8]}};
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dat_o <= {4{pc[15:8]}};
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state <= BYTE_IRQ5;
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state <= BYTE_IRQ5;
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end
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end
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BYTE_IRQ5:
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BYTE_IRQ5:
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if (ack_i) begin
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if (ack_i) begin
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state <= BYTE_IRQ6;
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retstate <= BYTE_IRQ6;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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sel_o <= 4'h0;
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sp <= sp_dec;
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sp <= sp_dec;
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if (dhit) begin
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if (dhit) begin
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wrsel <= sel_o;
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wrsel <= sel_o;
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wr <= 1'b1;
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wr <= 1'b1;
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end
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end
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state <= BYTE_IRQ6;
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else if (write_allocate) begin
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state <= WAIT_DHIT;
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dmiss <= `TRUE;
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end
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end
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end
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BYTE_IRQ6:
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BYTE_IRQ6:
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begin
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begin
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radr <= {24'h1,sp[7:2]};
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radr <= {24'h1,sp[7:2]};
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radr2LSB <= sp[1:0];
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radr2LSB <= sp[1:0];
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Line 137... |
dat_o <= {4{pc[7:0]}};
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dat_o <= {4{pc[7:0]}};
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state <= BYTE_IRQ7;
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state <= BYTE_IRQ7;
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end
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end
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BYTE_IRQ7:
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BYTE_IRQ7:
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if (ack_i) begin
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if (ack_i) begin
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state <= BYTE_IRQ8;
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retstate <= BYTE_IRQ8;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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sel_o <= 4'h0;
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sp <= sp_dec;
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sp <= sp_dec;
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if (dhit) begin
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if (dhit) begin
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wrsel <= sel_o;
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wrsel <= sel_o;
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wr <= 1'b1;
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wr <= 1'b1;
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end
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end
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state <= BYTE_IRQ8;
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else if (write_allocate) begin
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state <= WAIT_DHIT;
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dmiss <= `TRUE;
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end
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end
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end
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BYTE_IRQ8:
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BYTE_IRQ8:
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begin
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begin
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radr <= {24'h1,sp[7:2]};
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radr <= {24'h1,sp[7:2]};
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radr2LSB <= sp[1:0];
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radr2LSB <= sp[1:0];
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Line 175... |
dat_o <= {4{sr8[7:0]}};
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dat_o <= {4{sr8[7:0]}};
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state <= BYTE_IRQ9;
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state <= BYTE_IRQ9;
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end
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end
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BYTE_IRQ9:
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BYTE_IRQ9:
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if (ack_i) begin
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if (ack_i) begin
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state <= BYTE_JMP_IND1;
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retstate <= BYTE_JMP_IND1;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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sel_o <= 4'h0;
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sp <= sp_dec;
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sp <= sp_dec;
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if (dhit) begin
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if (dhit) begin
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wrsel <= sel_o;
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wrsel <= sel_o;
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wr <= 1'b1;
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wr <= 1'b1;
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end
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end
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else if (write_allocate) begin
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state <= WAIT_DHIT;
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dmiss <= `TRUE;
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end
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pc[31:16] <= 16'h0000;
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pc[31:16] <= 16'h0000;
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radr <= vect[31:2];
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radr <= vect[31:2];
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radr2LSB <= vect[1:0];
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radr2LSB <= vect[1:0];
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state <= BYTE_JMP_IND1;
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end
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end
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No newline at end of file
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No newline at end of file
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