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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_irq.v] - Diff between revs 10 and 13

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Rev 10 Rev 13
Line 41... Line 41... 
                        dmiss <= `TRUE;
 
                        dmiss <= `TRUE;
 
                end
 
                end
 
        end
 
        end
 
BYTE_IRQ2:
 
BYTE_IRQ2:
 
        begin
 
        begin
 
                radr <= {24'h1,sp[7:2]};
 
                radr <= {spage[31:8],sp[7:2]};
 
                radr2LSB <= sp[1:0];
 
                radr2LSB <= sp[1:0];
 
                wadr <= {24'h1,sp[7:2]};
 
                wadr <= {spage[31:8],sp[7:2]};
 
                wadr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wdat <= {4{pc[23:16]}};
 
                wdat <= {4{pc[23:16]}};
 
                cyc_o <= 1'b1;
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                we_o <= 1'b1;
 
                we_o <= 1'b1;
Line 55... Line 55... 
                2'd0:   sel_o <= 4'b0001;
 
                2'd0:   sel_o <= 4'b0001;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd3:   sel_o <= 4'b1000;
 
                2'd3:   sel_o <= 4'b1000;
 
                endcase
 
                endcase
 
                adr_o <= {24'h1,sp[7:2],2'b00};
 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                dat_o <= {4{pc[23:16]}};
 
                dat_o <= {4{pc[23:16]}};
 
                state <= BYTE_IRQ3;
 
                state <= BYTE_IRQ3;
 
        end
 
        end
 
BYTE_IRQ3:
 
BYTE_IRQ3:
 
        if (ack_i) begin
 
        if (ack_i) begin
Line 79... Line 79... 
                        dmiss <= `TRUE;
 
                        dmiss <= `TRUE;
 
                end
 
                end
 
        end
 
        end
 
BYTE_IRQ4:
 
BYTE_IRQ4:
 
        begin
 
        begin
 
                radr <= {24'h1,sp[7:2]};
 
                radr <= {spage[31:8],sp[7:2]};
 
                radr2LSB <= sp[1:0];
 
                radr2LSB <= sp[1:0];
 
                wadr <= {24'h1,sp[7:2]};
 
                wadr <= {spage[31:8],sp[7:2]};
 
                wadr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wdat <= {4{pc[15:8]}};
 
                wdat <= {4{pc[15:8]}};
 
                cyc_o <= 1'b1;
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                we_o <= 1'b1;
 
                we_o <= 1'b1;
Line 93... Line 93... 
                2'd0:   sel_o <= 4'b0001;
 
                2'd0:   sel_o <= 4'b0001;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd3:   sel_o <= 4'b1000;
 
                2'd3:   sel_o <= 4'b1000;
 
                endcase
 
                endcase
 
                adr_o <= {24'h1,sp[7:2],2'b00};
 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                dat_o <= {4{pc[15:8]}};
 
                dat_o <= {4{pc[15:8]}};
 
                state <= BYTE_IRQ5;
 
                state <= BYTE_IRQ5;
 
        end
 
        end
 
BYTE_IRQ5:
 
BYTE_IRQ5:
 
        if (ack_i) begin
 
        if (ack_i) begin
Line 117... Line 117... 
                        dmiss <= `TRUE;
 
                        dmiss <= `TRUE;
 
                end
 
                end
 
        end
 
        end
 
BYTE_IRQ6:
 
BYTE_IRQ6:
 
        begin
 
        begin
 
                radr <= {24'h1,sp[7:2]};
 
                radr <= {spage[31:8],sp[7:2]};
 
                radr2LSB <= sp[1:0];
 
                radr2LSB <= sp[1:0];
 
                wadr <= {24'h1,sp[7:2]};
 
                wadr <= {spage[31:8],sp[7:2]};
 
                wadr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wdat <= {4{pc[7:0]}};
 
                wdat <= {4{pc[7:0]}};
 
                cyc_o <= 1'b1;
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                we_o <= 1'b1;
 
                we_o <= 1'b1;
Line 131... Line 131... 
                2'd0:   sel_o <= 4'b0001;
 
                2'd0:   sel_o <= 4'b0001;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd3:   sel_o <= 4'b1000;
 
                2'd3:   sel_o <= 4'b1000;
 
                endcase
 
                endcase
 
                adr_o <= {24'h1,sp[7:2],2'b00};
 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                dat_o <= {4{pc[7:0]}};
 
                dat_o <= {4{pc[7:0]}};
 
                state <= BYTE_IRQ7;
 
                state <= BYTE_IRQ7;
 
        end
 
        end
 
BYTE_IRQ7:
 
BYTE_IRQ7:
 
        if (ack_i) begin
 
        if (ack_i) begin
Line 155... Line 155... 
                        dmiss <= `TRUE;
 
                        dmiss <= `TRUE;
 
                end
 
                end
 
        end
 
        end
 
BYTE_IRQ8:
 
BYTE_IRQ8:
 
        begin
 
        begin
 
                radr <= {24'h1,sp[7:2]};
 
                radr <= {spage[31:8],sp[7:2]};
 
                radr2LSB <= sp[1:0];
 
                radr2LSB <= sp[1:0];
 
                wadr <= {24'h1,sp[7:2]};
 
                wadr <= {spage[31:8],sp[7:2]};
 
                wadr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wdat <= {4{sr8[7:0]}};
 
                wdat <= {4{sr8[7:0]}};
 
                cyc_o <= 1'b1;
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                we_o <= 1'b1;
 
                we_o <= 1'b1;
Line 169... Line 169... 
                2'd0:   sel_o <= 4'b0001;
 
                2'd0:   sel_o <= 4'b0001;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd3:   sel_o <= 4'b1000;
 
                2'd3:   sel_o <= 4'b1000;
 
                endcase
 
                endcase
 
                adr_o <= {24'h1,sp[7:2],2'b00};
 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                dat_o <= {4{sr8[7:0]}};
 
                dat_o <= {4{sr8[7:0]}};
 
                state <= BYTE_IRQ9;
 
                state <= BYTE_IRQ9;
 
        end
 
        end
 
BYTE_IRQ9:
 
BYTE_IRQ9:
 
        if (ack_i) begin
 
        if (ack_i) begin

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