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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_irq.v] - Diff between revs 13 and 21
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| Rev 13 |
Rev 21 |
| Line 23... |
Line 23... |
// IRQ processing states for 65C02 emulation mode
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// IRQ processing states for 65C02 emulation mode
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// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.
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// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.
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//
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//
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BYTE_IRQ1:
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BYTE_IRQ1:
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if (ack_i) begin
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if (ack_i) begin
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ir <= 64'd0;
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state <= BYTE_IRQ2;
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state <= BYTE_IRQ2;
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retstate <= BYTE_IRQ2;
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retstate <= BYTE_IRQ2;
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cyc_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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we_o <= 1'b0;
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