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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_irq.v] - Diff between revs 13 and 21

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Rev 13 Rev 21
Line 23... Line 23...
// IRQ processing states for 65C02 emulation mode
// IRQ processing states for 65C02 emulation mode
// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.
// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.
//
//
BYTE_IRQ1:
BYTE_IRQ1:
        if (ack_i) begin
        if (ack_i) begin
 
                ir <= 64'd0;
                state <= BYTE_IRQ2;
                state <= BYTE_IRQ2;
                retstate <= BYTE_IRQ2;
                retstate <= BYTE_IRQ2;
                cyc_o <= 1'b0;
                cyc_o <= 1'b0;
                stb_o <= 1'b0;
                stb_o <= 1'b0;
                we_o <= 1'b0;
                we_o <= 1'b0;

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