URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_irq.v] - Diff between revs 21 and 30

Rev 21	Rev 30
Line 23...	Line 23...
`// IRQ processing states for 65C02 emulation mode`	`// IRQ processing states for 65C02 emulation mode`
`// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.`	`// The high order PC[31:16] is set to zero, forcing the IRQ routine to be in bank zero.`
`//`	`//`
`BYTE_IRQ1:`	`BYTE_IRQ1:`
`if (ack_i) begin`	`if (ack_i) begin`
`ir <= 64'd0;`
`state <= BYTE_IRQ2;`	`state <= BYTE_IRQ2;`
`retstate <= BYTE_IRQ2;`	`retstate <= BYTE_IRQ2;`
`cyc_o <= 1'b0;`	`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`	`stb_o <= 1'b0;`
`we_o <= 1'b0;`	`we_o <= 1'b0;`
Line 176...	Line 175...
`dat_o <= {4{sr8[7:0]}};`	`dat_o <= {4{sr8[7:0]}};`
`state <= BYTE_IRQ9;`	`state <= BYTE_IRQ9;`
`end`	`end`
`BYTE_IRQ9:`	`BYTE_IRQ9:`
`if (ack_i) begin`	`if (ack_i) begin`
`state <= BYTE_JMP_IND1;`	load_what <= `PC_70;
`retstate <= BYTE_JMP_IND1;`	`state <= LOAD_MAC1;`
	`retstate <= LOAD_MAC1;`
`cyc_o <= 1'b0;`	`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`	`stb_o <= 1'b0;`
`we_o <= 1'b0;`	`we_o <= 1'b0;`
`sel_o <= 4'h0;`	`sel_o <= 4'h0;`
`sp <= sp_dec;`	`sp <= sp_dec;`