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Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_iy.v] - Diff between revs 20 and 21

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Rev 20 Rev 21
Line 46... Line 46...
                ia[7:0] <= dati;
                ia[7:0] <= dati;
                radr <= radr34p1[33:2];
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                radr2LSB <= radr34p1[1:0];
                state <= BYTE_IY3;
                state <= BYTE_IY3;
        end
        end
 
        else if (err_i) begin
 
                lock_o <= 1'b0;
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                we_o <= 1'b0;
 
                sel_o <= 4'h0;
 
                adr_o <= 34'h0;
 
                dat_o <= 32'h0;
 
                state <= BUS_ERROR;
 
        end
BYTE_IY3:
BYTE_IY3:
        if (unCachedData) begin
        if (unCachedData) begin
                cyc_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hf;
                sel_o <= 4'hf;
Line 75... Line 85...
                ia[31:16] <= 16'h0000;
                ia[31:16] <= 16'h0000;
                radr <= radr34p1[33:2];
                radr <= radr34p1[33:2];
                radr2LSB <= radr34p1[1:0];
                radr2LSB <= radr34p1[1:0];
                state <= BYTE_IY5;
                state <= BYTE_IY5;
        end
        end
 
        else if (err_i) begin
 
                lock_o <= 1'b0;
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                we_o <= 1'b0;
 
                sel_o <= 4'h0;
 
                adr_o <= 34'h0;
 
                dat_o <= 32'h0;
 
                state <= BUS_ERROR;
 
        end
BYTE_IY5:
BYTE_IY5:
        begin
        begin
                radr <= iapy8[31:2];
                radr <= iapy8[31:2];
                radr2LSB <= iapy8[1:0];
                radr2LSB <= iapy8[1:0];
                $display("IY addr: %h", iapy8);
                $display("IY addr: %h", iapy8);

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