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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsl.v] - Diff between revs 10 and 13

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Rev 10 Rev 13
Line 37... Line 37... 
                        dmiss <= `TRUE;
 
                        dmiss <= `TRUE;
 
                end
 
                end
 
        end
 
        end
 
BYTE_JSL2:
 
BYTE_JSL2:
 
        begin
 
        begin
 
                radr <= {24'h1,sp[7:2]};
 
                radr <= {spage[31:8],sp[7:2]};
 
                wadr <= {24'h1,sp[7:2]};
 
                wadr <= {spage[31:8],sp[7:2]};
 
                radr2LSB <= sp[1:0];
 
                radr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wdat <= {4{pcp4[23:16]}};
 
                wdat <= {4{pcp4[23:16]}};
 
                cyc_o <= 1'b1;
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                stb_o <= 1'b1;
Line 51... Line 51... 
                2'd0:   sel_o <= 4'b0001;
 
                2'd0:   sel_o <= 4'b0001;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd3:   sel_o <= 4'b1000;
 
                2'd3:   sel_o <= 4'b1000;
 
                endcase
 
                endcase
 
                adr_o <= {24'h1,sp[7:2],2'b00};
 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                dat_o <= {4{pcp4[23:16]}};
 
                dat_o <= {4{pcp4[23:16]}};
 
                sp <= sp_dec;
 
                sp <= sp_dec;
 
                state <= BYTE_JSL3;
 
                state <= BYTE_JSL3;
 
        end
 
        end
 
BYTE_JSL3:
 
BYTE_JSL3:
Line 75... Line 75... 
                        dmiss <= `TRUE;
 
                        dmiss <= `TRUE;
 
                end
 
                end
 
        end
 
        end
 
BYTE_JSL4:
 
BYTE_JSL4:
 
        begin
 
        begin
 
                radr <= {24'h1,sp[7:2]};
 
                radr <= {spage[31:8],sp[7:2]};
 
                wadr <= {24'h1,sp[7:2]};
 
                wadr <= {spage[31:8],sp[7:2]};
 
                radr2LSB <= sp[1:0];
 
                radr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wdat <= {4{pcp4[15:8]}};
 
                wdat <= {4{pcp4[15:8]}};
 
                cyc_o <= 1'b1;
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                stb_o <= 1'b1;
Line 89... Line 89... 
                2'd0:   sel_o <= 4'b0001;
 
                2'd0:   sel_o <= 4'b0001;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd3:   sel_o <= 4'b1000;
 
                2'd3:   sel_o <= 4'b1000;
 
                endcase
 
                endcase
 
                adr_o <= {24'h1,sp[7:2],2'b00};
 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                dat_o <= {4{pcp4[15:8]}};
 
                dat_o <= {4{pcp4[15:8]}};
 
                sp <= sp_dec;
 
                sp <= sp_dec;
 
                state <= BYTE_JSL5;
 
                state <= BYTE_JSL5;
 
        end
 
        end
 
BYTE_JSL5:
 
BYTE_JSL5:
Line 113... Line 113... 
                        dmiss <= `TRUE;
 
                        dmiss <= `TRUE;
 
                end
 
                end
 
        end
 
        end
 
BYTE_JSL6:
 
BYTE_JSL6:
 
        begin
 
        begin
 
                radr <= {24'h1,sp[7:2]};
 
                radr <= {spage[31:8],sp[7:2]};
 
                wadr <= {24'h1,sp[7:2]};
 
                wadr <= {spage[31:8],sp[7:2]};
 
                radr2LSB <= sp[1:0];
 
                radr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wadr2LSB <= sp[1:0];
 
                wdat <= {4{pcp4[7:0]}};
 
                wdat <= {4{pcp4[7:0]}};
 
                cyc_o <= 1'b1;
 
                cyc_o <= 1'b1;
 
                stb_o <= 1'b1;
 
                stb_o <= 1'b1;
Line 127... Line 127... 
                2'd0:   sel_o <= 4'b0001;
 
                2'd0:   sel_o <= 4'b0001;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd1:   sel_o <= 4'b0010;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd2:   sel_o <= 4'b0100;
 
                2'd3:   sel_o <= 4'b1000;
 
                2'd3:   sel_o <= 4'b1000;
 
                endcase
 
                endcase
 
                adr_o <= {24'h1,sp[7:2],2'b00};
 
                adr_o <= {spage[31:8],sp[7:2],2'b00};
 
                dat_o <= {4{pcp4[7:0]}};
 
                dat_o <= {4{pcp4[7:0]}};
 
                sp <= sp_dec;
 
                sp <= sp_dec;
 
                state <= BYTE_JSL7;
 
                state <= BYTE_JSL7;
 
        end
 
        end
 
BYTE_JSL7:
 
BYTE_JSL7:

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