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Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsl.v] - Diff between revs 13 and 21

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Rev 13	Rev 21
Line 35...	Line 35...
`else if (write_allocate) begin`	`else if (write_allocate) begin`
`state <= WAIT_DHIT;`	`state <= WAIT_DHIT;`
dmiss <= `TRUE;	dmiss <= `TRUE;
`end`	`end`
`end`	`end`
	`else if (err_i) begin`
	`lock_o <= 1'b0;`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`we_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'h0;`
	`dat_o <= 32'h0;`
	`state <= BUS_ERROR;`
	`end`
`BYTE_JSL2:`	`BYTE_JSL2:`
`begin`	`begin`
`radr <= {spage[31:8],sp[7:2]};`	`radr <= {spage[31:8],sp[7:2]};`
`wadr <= {spage[31:8],sp[7:2]};`	`wadr <= {spage[31:8],sp[7:2]};`
`radr2LSB <= sp[1:0];`	`radr2LSB <= sp[1:0];`
Line 73...	Line 83...
`else if (write_allocate) begin`	`else if (write_allocate) begin`
`state <= WAIT_DHIT;`	`state <= WAIT_DHIT;`
dmiss <= `TRUE;	dmiss <= `TRUE;
`end`	`end`
`end`	`end`
	`else if (err_i) begin`
	`lock_o <= 1'b0;`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`we_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'h0;`
	`dat_o <= 32'h0;`
	`state <= BUS_ERROR;`
	`end`
`BYTE_JSL4:`	`BYTE_JSL4:`
`begin`	`begin`
`radr <= {spage[31:8],sp[7:2]};`	`radr <= {spage[31:8],sp[7:2]};`
`wadr <= {spage[31:8],sp[7:2]};`	`wadr <= {spage[31:8],sp[7:2]};`
`radr2LSB <= sp[1:0];`	`radr2LSB <= sp[1:0];`
Line 111...	Line 131...
`else if (write_allocate) begin`	`else if (write_allocate) begin`
`state <= WAIT_DHIT;`	`state <= WAIT_DHIT;`
dmiss <= `TRUE;	dmiss <= `TRUE;
`end`	`end`
`end`	`end`
	`else if (err_i) begin`
	`lock_o <= 1'b0;`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`we_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'h0;`
	`dat_o <= 32'h0;`
	`state <= BUS_ERROR;`
	`end`
`BYTE_JSL6:`	`BYTE_JSL6:`
`begin`	`begin`
`radr <= {spage[31:8],sp[7:2]};`	`radr <= {spage[31:8],sp[7:2]};`
`wadr <= {spage[31:8],sp[7:2]};`	`wadr <= {spage[31:8],sp[7:2]};`
`radr2LSB <= sp[1:0];`	`radr2LSB <= sp[1:0];`
Line 150...	Line 180...
`state <= WAIT_DHIT;`	`state <= WAIT_DHIT;`
dmiss <= `TRUE;	dmiss <= `TRUE;
`end`	`end`
`pc <= ir[39:8];`	`pc <= ir[39:8];`
`end`	`end`
	`else if (err_i) begin`
	`lock_o <= 1'b0;`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`we_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'h0;`
	`dat_o <= 32'h0;`
	`state <= BUS_ERROR;`
	`end`

`No newline at end of file`	`No newline at end of file`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsl.v] - Diff between revs 13 and 21