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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_jsr.v] - Diff between revs 13 and 20
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| Rev 13 |
Rev 20 |
| Line 74... |
Line 74... |
else if (write_allocate) begin
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else if (write_allocate) begin
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state <= WAIT_DHIT;
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state <= WAIT_DHIT;
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dmiss <= `TRUE;
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dmiss <= `TRUE;
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end
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end
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end
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end
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BYTE_JSR_INDX1:
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if (ack_i) begin
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state <= BYTE_JSR_INDX2;
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retstate <= BYTE_JSR_INDX2;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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if (dhit) begin
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wrsel <= sel_o;
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wr <= 1'b1;
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end
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else if (write_allocate) begin
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state <= WAIT_DHIT;
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dmiss <= `TRUE;
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end
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end
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BYTE_JSR_INDX2:
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begin
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radr <= {spage[31:8],sp[7:2]};
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wadr <= {spage[31:8],sp[7:2]};
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radr2LSB <= sp[1:0];
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wadr2LSB <= sp[1:0];
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wdat <= {4{pcp2[7:0]}};
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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we_o <= 1'b1;
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case(sp[1:0])
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2'd0: sel_o <= 4'b0001;
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2'd1: sel_o <= 4'b0010;
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2'd2: sel_o <= 4'b0100;
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2'd3: sel_o <= 4'b1000;
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endcase
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adr_o <= {spage[31:8],sp[7:2],2'b00};
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dat_o <= {4{pcp2[7:0]}};
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sp <= sp_dec;
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state <= BYTE_JSR_INDX3;
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end
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BYTE_JSR_INDX3:
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if (ack_i) begin
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state <= BYTE_JMP_IND1;
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retstate <= BYTE_JMP_IND1;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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adr_o <= 34'd0;
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dat_o <= 32'd0;
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radr <= absx_address[15:2];
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radr2LSB <= absx_address[1:0];
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if (dhit) begin
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wrsel <= sel_o;
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wr <= 1'b1;
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end
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else if (write_allocate) begin
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state <= WAIT_DHIT;
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dmiss <= `TRUE;
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end
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end
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