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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_plp.v] - Diff between revs 5 and 10

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// ============================================================================
 
//        __
 
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
 
//    \  __ /    All rights reserved.
 
//     \/_//     robfinch<remove>@opencores.org
 
//       ||
 
//
 
// This source file is free software: you can redistribute it and/or modify 
 
// it under the terms of the GNU Lesser General Public License as published 
 
// by the Free Software Foundation, either version 3 of the License, or     
 
// (at your option) any later version.                                      
 
//                                                                          
 
// This source file is distributed in the hope that it will be useful,      
 
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
 
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
 
// GNU General Public License for more details.                             
 
//                                                                          
 
// You should have received a copy of the GNU General Public License        
 
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
 
//                                                                          
 
// ============================================================================
 
//
BYTE_PLP1:
BYTE_PLP1:
        if (unCachedData) begin
        if (unCachedData) begin
                cyc_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                sel_o <= 4'hF;

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