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Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rti.v] - Diff between revs 10 and 13

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Rev 10 Rev 13
Line 37... Line 37... 
                df <= rdat8[3];
 
                df <= rdat8[3];
 
                bf <= rdat8[4];
 
                bf <= rdat8[4];
 
                vf <= rdat8[6];
 
                vf <= rdat8[6];
 
                nf <= rdat8[7];
 
                nf <= rdat8[7];
 
                sp <= sp_inc;
 
                sp <= sp_inc;
 
                radr <= {24'h1,sp_inc[7:2]};
 
                radr <= {spage[31:8],sp_inc[7:2]};
 
                radr2LSB <= sp_inc[1:0];
 
                radr2LSB <= sp_inc[1:0];
 
                state <= BYTE_RTI1;
 
                state <= BYTE_RTI1;
 
        end
 
        end
 
        else
 
        else
 
                dmiss <= `TRUE;
 
                dmiss <= `TRUE;
Line 56... Line 56... 
                df <= dati[3];
 
                df <= dati[3];
 
                bf <= dati[4];
 
                bf <= dati[4];
 
                vf <= dati[6];
 
                vf <= dati[6];
 
                nf <= dati[7];
 
                nf <= dati[7];
 
                sp <= sp_inc;
 
                sp <= sp_inc;
 
                radr <= {24'h1,sp_inc[7:2]};
 
                radr <= {spage[31:8],sp_inc[7:2]};
 
                radr2LSB <= sp_inc[1:0];
 
                radr2LSB <= sp_inc[1:0];
 
                state <= BYTE_RTI1;
 
                state <= BYTE_RTI1;
 
        end
 
        end
 
BYTE_RTI1:
 
BYTE_RTI1:
 
        if (unCachedData) begin
 
        if (unCachedData) begin
Line 69... Line 69... 
                sel_o <= 4'hF;
 
                sel_o <= 4'hF;
 
                adr_o <= {radr,2'b00};
 
                adr_o <= {radr,2'b00};
 
                state <= RTI2;
 
                state <= RTI2;
 
        end
 
        end
 
        else if (dhit) begin
 
        else if (dhit) begin
 
                radr <= {24'h1,sp_inc[7:2]};
 
                radr <= {spage[31:8],sp_inc[7:2]};
 
                radr2LSB <= sp_inc[1:0];
 
                radr2LSB <= sp_inc[1:0];
 
                sp <= sp_inc;
 
                sp <= sp_inc;
 
                pc[7:0] <= rdat8;
 
                pc[7:0] <= rdat8;
 
                state <= BYTE_RTI3;
 
                state <= BYTE_RTI3;
 
        end
 
        end
Line 83... Line 83... 
        if (ack_i) begin
 
        if (ack_i) begin
 
                cyc_o <= 1'b0;
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                sel_o <= 4'h0;
 
                sel_o <= 4'h0;
 
                adr_o <= 34'h0;
 
                adr_o <= 34'h0;
 
                radr <= {24'h1,sp_inc[7:2]};
 
                radr <= {spage[31:8],sp_inc[7:2]};
 
                radr2LSB <= sp_inc[1:0];
 
                radr2LSB <= sp_inc[1:0];
 
                sp <= sp_inc;
 
                sp <= sp_inc;
 
                pc[7:0] <= dati;
 
                pc[7:0] <= dati;
 
                state <= BYTE_RTI3;
 
                state <= BYTE_RTI3;
 
        end
 
        end
Line 98... Line 98... 
                sel_o <= 4'hF;
 
                sel_o <= 4'hF;
 
                adr_o <= {radr,2'b00};
 
                adr_o <= {radr,2'b00};
 
                state <= BYTE_RTI4;
 
                state <= BYTE_RTI4;
 
        end
 
        end
 
        else if (dhit) begin
 
        else if (dhit) begin
 
                radr <= {24'h1,sp_inc[7:2]};
 
                radr <= {spage[31:8],sp_inc[7:2]};
 
                radr2LSB <= sp_inc[1:0];
 
                radr2LSB <= sp_inc[1:0];
 
                sp <= sp_inc;
 
                sp <= sp_inc;
 
                pc[15:8] <= rdat8;
 
                pc[15:8] <= rdat8;
 
                state <= BYTE_RTI5;
 
                state <= BYTE_RTI5;
 
        end
 
        end
Line 112... Line 112... 
        if (ack_i) begin
 
        if (ack_i) begin
 
                cyc_o <= 1'b0;
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                sel_o <= 4'h0;
 
                sel_o <= 4'h0;
 
                adr_o <= 34'h0;
 
                adr_o <= 34'h0;
 
                radr <= {24'h1,sp_inc[7:2]};
 
                radr <= {spage[31:8],sp_inc[7:2]};
 
                radr2LSB <= sp_inc[1:0];
 
                radr2LSB <= sp_inc[1:0];
 
                sp <= sp_inc;
 
                sp <= sp_inc;
 
                pc[15:8] <= dati;
 
                pc[15:8] <= dati;
 
                state <= BYTE_RTI5;
 
                state <= BYTE_RTI5;
 
        end
 
        end
Line 127... Line 127... 
                sel_o <= 4'hF;
 
                sel_o <= 4'hF;
 
                adr_o <= {radr,2'b00};
 
                adr_o <= {radr,2'b00};
 
                state <= BYTE_RTI6;
 
                state <= BYTE_RTI6;
 
        end
 
        end
 
        else if (dhit) begin
 
        else if (dhit) begin
 
                radr <= {24'h1,sp_inc[7:2]};
 
                radr <= {spage[31:8],sp_inc[7:2]};
 
                radr2LSB <= sp_inc[1:0];
 
                radr2LSB <= sp_inc[1:0];
 
                sp <= sp_inc;
 
                sp <= sp_inc;
 
                pc[23:16] <= rdat8;
 
                pc[23:16] <= rdat8;
 
                state <= BYTE_RTI7;
 
                state <= BYTE_RTI7;
 
        end
 
        end
Line 141... Line 141... 
        if (ack_i) begin
 
        if (ack_i) begin
 
                cyc_o <= 1'b0;
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                sel_o <= 4'h0;
 
                sel_o <= 4'h0;
 
                adr_o <= 34'h0;
 
                adr_o <= 34'h0;
 
                radr <= {24'h1,sp_inc[7:2]};
 
                radr <= {spage[31:8],sp_inc[7:2]};
 
                radr2LSB <= sp_inc[1:0];
 
                radr2LSB <= sp_inc[1:0];
 
                sp <= sp_inc;
 
                sp <= sp_inc;
 
                pc[23:16] <= dati;
 
                pc[23:16] <= dati;
 
                state <= BYTE_RTI7;
 
                state <= BYTE_RTI7;
 
        end
 
        end

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