URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rti.v] - Diff between revs 13 and 21

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Rev 13	Rev 21
Line 60...	Line 60...
`sp <= sp_inc;`	`sp <= sp_inc;`
`radr <= {spage[31:8],sp_inc[7:2]};`	`radr <= {spage[31:8],sp_inc[7:2]};`
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`state <= BYTE_RTI1;`	`state <= BYTE_RTI1;`
`end`	`end`
	`else if (err_i) begin`
	`lock_o <= 1'b0;`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`we_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'h0;`
	`dat_o <= 32'h0;`
	`state <= BUS_ERROR;`
	`end`
`BYTE_RTI1:`	`BYTE_RTI1:`
`if (unCachedData) begin`	`if (unCachedData) begin`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
`sel_o <= 4'hF;`	`sel_o <= 4'hF;`
Line 89...	Line 99...
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`	`sp <= sp_inc;`
`pc[7:0] <= dati;`	`pc[7:0] <= dati;`
`state <= BYTE_RTI3;`	`state <= BYTE_RTI3;`
`end`	`end`
	`else if (err_i) begin`
	`lock_o <= 1'b0;`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`we_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'h0;`
	`dat_o <= 32'h0;`
	`state <= BUS_ERROR;`
	`end`
`BYTE_RTI3:`	`BYTE_RTI3:`
`if (unCachedData) begin`	`if (unCachedData) begin`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
`sel_o <= 4'hF;`	`sel_o <= 4'hF;`
Line 118...	Line 138...
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`	`sp <= sp_inc;`
`pc[15:8] <= dati;`	`pc[15:8] <= dati;`
`state <= BYTE_RTI5;`	`state <= BYTE_RTI5;`
`end`	`end`
	`else if (err_i) begin`
	`lock_o <= 1'b0;`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`we_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'h0;`
	`dat_o <= 32'h0;`
	`state <= BUS_ERROR;`
	`end`
`BYTE_RTI5:`	`BYTE_RTI5:`
`if (unCachedData) begin`	`if (unCachedData) begin`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
`sel_o <= 4'hF;`	`sel_o <= 4'hF;`
Line 147...	Line 177...
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`	`sp <= sp_inc;`
`pc[23:16] <= dati;`	`pc[23:16] <= dati;`
`state <= BYTE_RTI7;`	`state <= BYTE_RTI7;`
`end`	`end`
	`else if (err_i) begin`
	`lock_o <= 1'b0;`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`we_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'h0;`
	`dat_o <= 32'h0;`
	`state <= BUS_ERROR;`
	`end`
`BYTE_RTI7:`	`BYTE_RTI7:`
`if (unCachedData) begin`	`if (unCachedData) begin`
`cyc_o <= 1'b1;`	`cyc_o <= 1'b1;`
`stb_o <= 1'b1;`	`stb_o <= 1'b1;`
`sel_o <= 4'hF;`	`sel_o <= 4'hF;`
Line 170...	Line 210...
`sel_o <= 4'h0;`	`sel_o <= 4'h0;`
`adr_o <= 34'h0;`	`adr_o <= 34'h0;`
`pc[31:24] <= dati;`	`pc[31:24] <= dati;`
`state <= IFETCH;`	`state <= IFETCH;`
`end`	`end`
	`else if (err_i) begin`
	`lock_o <= 1'b0;`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`we_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'h0;`
	`dat_o <= 32'h0;`
	`state <= BUS_ERROR;`
	`end`

`No newline at end of file`	`No newline at end of file`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rti.v] - Diff between revs 13 and 21