URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rts.v] - Diff between revs 10 and 13

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Rev 10	Rev 13
Line 29...	Line 29...
`sel_o <= 4'hF;`	`sel_o <= 4'hF;`
`adr_o <= {radr,2'b00};`	`adr_o <= {radr,2'b00};`
`state <= BYTE_RTS2;`	`state <= BYTE_RTS2;`
`end`	`end`
`else if (dhit) begin`	`else if (dhit) begin`
`radr <= {26'h1,sp_inc[7:2]};`	`radr <= {spage[31:8],sp_inc[7:2]};`
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`	`sp <= sp_inc;`
`pc[7:0] <= rdat8;`	`pc[7:0] <= rdat8;`
`state <= BYTE_RTS3;`	`state <= BYTE_RTS3;`
`end`	`end`
Line 43...	Line 43...
`if (ack_i) begin`	`if (ack_i) begin`
`cyc_o <= 1'b0;`	`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`	`stb_o <= 1'b0;`
`sel_o <= 4'h0;`	`sel_o <= 4'h0;`
`adr_o <= 34'h0;`	`adr_o <= 34'h0;`
`radr <= {26'h1,sp_inc[7:2]};`	`radr <= {spage[31:8],sp_inc[7:2]};`
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`	`sp <= sp_inc;`
`pc[7:0] <= dati;`	`pc[7:0] <= dati;`
`state <= BYTE_RTS3;`	`state <= BYTE_RTS3;`
`end`	`end`
Line 59...	Line 59...
`adr_o <= {radr,2'b00};`	`adr_o <= {radr,2'b00};`
`state <= BYTE_RTS4;`	`state <= BYTE_RTS4;`
`end`	`end`
`else if (dhit) begin`	`else if (dhit) begin`
if (ir[7:0]==`RTL) begin	if (ir[7:0]==`RTL) begin
`radr <= {26'h1,sp_inc[7:2]};`	`radr <= {spage[31:8],sp_inc[7:2]};`
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`	`sp <= sp_inc;`
`end`	`end`
`pc[15:8] <= rdat8;`	`pc[15:8] <= rdat8;`
`state <= BYTE_RTS5;`	`state <= BYTE_RTS5;`
Line 76...	Line 76...
`stb_o <= 1'b0;`	`stb_o <= 1'b0;`
`sel_o <= 4'h0;`	`sel_o <= 4'h0;`
`adr_o <= 34'h0;`	`adr_o <= 34'h0;`
`pc[15:8] <= dati;`	`pc[15:8] <= dati;`
if (ir[7:0]==`RTL) begin	if (ir[7:0]==`RTL) begin
`radr <= {26'h1,sp_inc[7:2]};`	`radr <= {spage[31:8],sp_inc[7:2]};`
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`	`sp <= sp_inc;`
`end`	`end`
`state <= BYTE_RTS5;`	`state <= BYTE_RTS5;`
`end`	`end`
Line 96...	Line 96...
`sel_o <= 4'hF;`	`sel_o <= 4'hF;`
`adr_o <= {radr,2'b00};`	`adr_o <= {radr,2'b00};`
`state <= BYTE_RTS6;`	`state <= BYTE_RTS6;`
`end`	`end`
`else if (dhit) begin`	`else if (dhit) begin`
`radr <= {26'h1,sp_inc[7:2]};`	`radr <= {spage[31:8],sp_inc[7:2]};`
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`	`sp <= sp_inc;`
`pc[23:16] <= rdat8;`	`pc[23:16] <= rdat8;`
`state <= BYTE_RTS7;`	`state <= BYTE_RTS7;`
`end`	`end`
Line 112...	Line 112...
`cyc_o <= 1'b0;`	`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`	`stb_o <= 1'b0;`
`sel_o <= 4'h0;`	`sel_o <= 4'h0;`
`adr_o <= 34'h0;`	`adr_o <= 34'h0;`
`pc[23:16] <= dati;`	`pc[23:16] <= dati;`
`radr <= {26'h1,sp_inc[7:2]};`	`radr <= {spage[31:8],sp_inc[7:2]};`
`radr2LSB <= sp_inc[1:0];`	`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`	`sp <= sp_inc;`
`state <= BYTE_RTS7;`	`state <= BYTE_RTS7;`
`end`	`end`
`BYTE_RTS7:`	`BYTE_RTS7:`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rts.v] - Diff between revs 10 and 13