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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rts.v] - Diff between revs 13 and 21
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| Rev 13 |
Rev 21 |
| Line 49... |
Line 49... |
radr2LSB <= sp_inc[1:0];
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radr2LSB <= sp_inc[1:0];
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sp <= sp_inc;
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sp <= sp_inc;
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pc[7:0] <= dati;
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pc[7:0] <= dati;
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state <= BYTE_RTS3;
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state <= BYTE_RTS3;
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end
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end
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else if (err_i) begin
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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adr_o <= 34'h0;
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dat_o <= 32'h0;
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state <= BUS_ERROR;
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end
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BYTE_RTS3:
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BYTE_RTS3:
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if (unCachedData) begin
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if (unCachedData) begin
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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sel_o <= 4'hF;
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sel_o <= 4'hF;
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| Line 82... |
Line 92... |
radr2LSB <= sp_inc[1:0];
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radr2LSB <= sp_inc[1:0];
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sp <= sp_inc;
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sp <= sp_inc;
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end
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end
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state <= BYTE_RTS5;
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state <= BYTE_RTS5;
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end
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end
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else if (err_i) begin
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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adr_o <= 34'h0;
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dat_o <= 32'h0;
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state <= BUS_ERROR;
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end
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BYTE_RTS5:
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BYTE_RTS5:
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if (ir[7:0]!=`RTL) begin
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if (ir[7:0]!=`RTL) begin
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pc <= pc + 32'd1;
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pc <= pc + 32'd1;
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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| Line 117... |
Line 137... |
radr <= {spage[31:8],sp_inc[7:2]};
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radr <= {spage[31:8],sp_inc[7:2]};
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radr2LSB <= sp_inc[1:0];
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radr2LSB <= sp_inc[1:0];
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sp <= sp_inc;
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sp <= sp_inc;
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state <= BYTE_RTS7;
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state <= BYTE_RTS7;
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end
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end
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else if (err_i) begin
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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adr_o <= 34'h0;
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dat_o <= 32'h0;
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state <= BUS_ERROR;
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end
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BYTE_RTS7:
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BYTE_RTS7:
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if (unCachedData) begin
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if (unCachedData) begin
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cyc_o <= 1'b1;
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cyc_o <= 1'b1;
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stb_o <= 1'b1;
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stb_o <= 1'b1;
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sel_o <= 4'hF;
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sel_o <= 4'hF;
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| Line 140... |
Line 170... |
sel_o <= 4'h0;
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sel_o <= 4'h0;
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adr_o <= 34'h0;
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adr_o <= 34'h0;
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pc[31:24] <= dati;
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pc[31:24] <= dati;
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state <= BYTE_RTS9;
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state <= BYTE_RTS9;
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end
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end
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else if (err_i) begin
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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we_o <= 1'b0;
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sel_o <= 4'h0;
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adr_o <= 34'h0;
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dat_o <= 32'h0;
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state <= BUS_ERROR;
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end
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BYTE_RTS9:
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BYTE_RTS9:
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begin
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begin
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pc <= pc + 32'd1;
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pc <= pc + 32'd1;
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state <= IFETCH;
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state <= IFETCH;
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end
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end
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