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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [byte_rts.v] - Diff between revs 13 and 21

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Rev 13 Rev 21
Line 49... Line 49...
                radr2LSB <= sp_inc[1:0];
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                sp <= sp_inc;
                pc[7:0] <= dati;
                pc[7:0] <= dati;
                state <= BYTE_RTS3;
                state <= BYTE_RTS3;
        end
        end
 
        else if (err_i) begin
 
                lock_o <= 1'b0;
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                we_o <= 1'b0;
 
                sel_o <= 4'h0;
 
                adr_o <= 34'h0;
 
                dat_o <= 32'h0;
 
                state <= BUS_ERROR;
 
        end
BYTE_RTS3:
BYTE_RTS3:
        if (unCachedData) begin
        if (unCachedData) begin
                cyc_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                sel_o <= 4'hF;
Line 82... Line 92...
                        radr2LSB <= sp_inc[1:0];
                        radr2LSB <= sp_inc[1:0];
                        sp <= sp_inc;
                        sp <= sp_inc;
                end
                end
                state <= BYTE_RTS5;
                state <= BYTE_RTS5;
        end
        end
 
        else if (err_i) begin
 
                lock_o <= 1'b0;
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                we_o <= 1'b0;
 
                sel_o <= 4'h0;
 
                adr_o <= 34'h0;
 
                dat_o <= 32'h0;
 
                state <= BUS_ERROR;
 
        end
BYTE_RTS5:
BYTE_RTS5:
        if (ir[7:0]!=`RTL) begin
        if (ir[7:0]!=`RTL) begin
                pc <= pc + 32'd1;
                pc <= pc + 32'd1;
                state <= IFETCH;
                state <= IFETCH;
        end
        end
Line 117... Line 137...
                radr <= {spage[31:8],sp_inc[7:2]};
                radr <= {spage[31:8],sp_inc[7:2]};
                radr2LSB <= sp_inc[1:0];
                radr2LSB <= sp_inc[1:0];
                sp <= sp_inc;
                sp <= sp_inc;
                state <= BYTE_RTS7;
                state <= BYTE_RTS7;
        end
        end
 
        else if (err_i) begin
 
                lock_o <= 1'b0;
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                we_o <= 1'b0;
 
                sel_o <= 4'h0;
 
                adr_o <= 34'h0;
 
                dat_o <= 32'h0;
 
                state <= BUS_ERROR;
 
        end
BYTE_RTS7:
BYTE_RTS7:
        if (unCachedData) begin
        if (unCachedData) begin
                cyc_o <= 1'b1;
                cyc_o <= 1'b1;
                stb_o <= 1'b1;
                stb_o <= 1'b1;
                sel_o <= 4'hF;
                sel_o <= 4'hF;
Line 140... Line 170...
                sel_o <= 4'h0;
                sel_o <= 4'h0;
                adr_o <= 34'h0;
                adr_o <= 34'h0;
                pc[31:24] <= dati;
                pc[31:24] <= dati;
                state <= BYTE_RTS9;
                state <= BYTE_RTS9;
        end
        end
 
        else if (err_i) begin
 
                lock_o <= 1'b0;
 
                cyc_o <= 1'b0;
 
                stb_o <= 1'b0;
 
                we_o <= 1'b0;
 
                sel_o <= 4'h0;
 
                adr_o <= 34'h0;
 
                dat_o <= 32'h0;
 
                state <= BUS_ERROR;
 
        end
BYTE_RTS9:
BYTE_RTS9:
        begin
        begin
                pc <= pc + 32'd1;
                pc <= pc + 32'd1;
                state <= IFETCH;
                state <= IFETCH;
        end
        end
 
 
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