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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Diff between revs 35 and 38

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Rev 35 Rev 38
Line 73... Line 73...
                isInsnCacheLoad <= `TRUE;
                isInsnCacheLoad <= `TRUE;
                wb_burst(6'd3,{pcp8[31:4],4'h0});
                wb_burst(6'd3,{pcp8[31:4],4'h0});
                state <= LOAD_ICACHE;
                state <= LOAD_ICACHE;
        end
        end
        else
        else
                state <= em ? BYTE_IFETCH : IFETCH;
                state <= ic_whence;     // return to where we came from
LOAD_ICACHE:
LOAD_ICACHE:
        if (ack_i) begin
        if (ack_i) begin
                if (adr_o[3:2]==2'b10)
                if (adr_o[3:2]==2'b10)
                        cti_o <= 3'b111;
                        cti_o <= 3'b111;
                if (adr_o[3:2]==2'b11) begin
                if (adr_o[3:2]==2'b11) begin
Line 126... Line 126...
                endcase
                endcase
                state <= LOAD_IBUF2;
                state <= LOAD_IBUF2;
        end
        end
LOAD_IBUF2:
LOAD_IBUF2:
        if (ack_i|err_i) begin
        if (ack_i|err_i) begin
                state <= em ? BYTE_IFETCH : LOAD_IBUF3;
                state <= ic_whence==BYTE_IFETCH ? BYTE_IFETCH : LOAD_IBUF3;
                case(pc[1:0])
                case(pc[1:0])
                2'd0:   ibuf[55:32] <= dat_i[23:0];
                2'd0:   ibuf[55:32] <= dat_i[23:0];
                2'd1:   ibuf[55:24] <= dat_i;
                2'd1:   ibuf[55:24] <= dat_i;
                2'd2:   ibuf[47:16] <= dat_i;
                2'd2:   ibuf[47:16] <= dat_i;
                2'd3:   ibuf[39:8] <= dat_i;
                2'd3:   ibuf[39:8] <= dat_i;

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