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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Diff between revs 35 and 38
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Rev 35 |
Rev 38 |
Line 73... |
Line 73... |
isInsnCacheLoad <= `TRUE;
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isInsnCacheLoad <= `TRUE;
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wb_burst(6'd3,{pcp8[31:4],4'h0});
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wb_burst(6'd3,{pcp8[31:4],4'h0});
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state <= LOAD_ICACHE;
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state <= LOAD_ICACHE;
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end
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end
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else
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else
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state <= em ? BYTE_IFETCH : IFETCH;
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state <= ic_whence; // return to where we came from
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LOAD_ICACHE:
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LOAD_ICACHE:
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if (ack_i) begin
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if (ack_i) begin
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if (adr_o[3:2]==2'b10)
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if (adr_o[3:2]==2'b10)
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cti_o <= 3'b111;
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cti_o <= 3'b111;
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if (adr_o[3:2]==2'b11) begin
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if (adr_o[3:2]==2'b11) begin
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Line 126... |
Line 126... |
endcase
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endcase
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state <= LOAD_IBUF2;
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state <= LOAD_IBUF2;
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end
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end
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LOAD_IBUF2:
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LOAD_IBUF2:
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if (ack_i|err_i) begin
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if (ack_i|err_i) begin
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state <= em ? BYTE_IFETCH : LOAD_IBUF3;
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state <= ic_whence==BYTE_IFETCH ? BYTE_IFETCH : LOAD_IBUF3;
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case(pc[1:0])
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case(pc[1:0])
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2'd0: ibuf[55:32] <= dat_i[23:0];
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2'd0: ibuf[55:32] <= dat_i[23:0];
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2'd1: ibuf[55:24] <= dat_i;
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2'd1: ibuf[55:24] <= dat_i;
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2'd2: ibuf[47:16] <= dat_i;
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2'd2: ibuf[47:16] <= dat_i;
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2'd3: ibuf[39:8] <= dat_i;
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2'd3: ibuf[39:8] <= dat_i;
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