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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Diff between revs 5 and 10
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// ============================================================================
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// ||
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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// ============================================================================
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//
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// Cache controller
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// Cache controller
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// Also takes care of loading the instruction buffer for non-cached access
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// Also takes care of loading the instruction buffer for non-cached access
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//
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//
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case(cstate)
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case(cstate)
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IDLE:
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IDLE:
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