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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Diff between revs 10 and 20
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| Rev 10 |
Rev 20 |
| Line 117... |
Line 117... |
end
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end
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LOAD_IBUF2:
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LOAD_IBUF2:
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if (ack_i) begin
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if (ack_i) begin
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case(pc[1:0])
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case(pc[1:0])
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2'd0: ibuf[55:32] <= dat_i[23:0];
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2'd0: ibuf[55:32] <= dat_i[23:0];
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2'd1: ibuf[55:24] <= dat_i[31:0];
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2'd1: ibuf[55:24] <= dat_i;
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2'd2: ibuf[47:16] <= dat_i[23:0];
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2'd2: ibuf[47:16] <= dat_i;
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2'd3: ibuf[39:8] <= dat_i;
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2'd3: ibuf[39:8] <= dat_i;
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endcase
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endcase
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cstate <= LOAD_IBUF3;
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cstate <= LOAD_IBUF3;
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adr_o <= adr_o + 34'd4;
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adr_o <= adr_o + 34'd4;
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end
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end
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