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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [cache_controller.v] - Diff between revs 20 and 21
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| Rev 20 |
Rev 21 |
| Line 87... |
Line 87... |
adr_o <= 34'h0;
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adr_o <= 34'h0;
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cstate <= IDLE;
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cstate <= IDLE;
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end
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end
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adr_o <= adr_o + 34'd4;
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adr_o <= adr_o + 34'd4;
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end
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end
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// What to do here
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else if (err_i) begin
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if (adr_o[3:2]==2'b11) begin
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dmiss <= `FALSE;
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isDataCacheLoad <= `FALSE;
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cti_o <= 3'b000;
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bl_o <= 6'd0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'h0;
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adr_o <= 34'h0;
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cstate <= IDLE;
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// The state machine will be waiting for a dhit.
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// Override the next state and send the processor to the bus error state.
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state <= BUS_ERROR;
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end
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adr_o <= adr_o + 34'd4;
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end
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LOAD_ICACHE:
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LOAD_ICACHE:
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if (ack_i) begin
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if (ack_i) begin
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if (adr_o[3:2]==2'b11) begin
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if (adr_o[3:2]==2'b11) begin
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imiss <= `FALSE;
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imiss <= `FALSE;
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isInsnCacheLoad <= `FALSE;
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isInsnCacheLoad <= `FALSE;
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| Line 102... |
Line 120... |
adr_o <= 34'd0;
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adr_o <= 34'd0;
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cstate <= IDLE;
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cstate <= IDLE;
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end
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end
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adr_o <= adr_o + 34'd4;
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adr_o <= adr_o + 34'd4;
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end
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end
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else if (err_i) begin
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if (adr_o[3:2]==2'b11) begin
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imiss <= `FALSE;
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isInsnCacheLoad <= `FALSE;
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cti_o <= 3'b000;
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bl_o <= 6'd0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'h0;
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adr_o <= 34'd0;
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state <= INSN_BUS_ERROR;
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cstate <= IDLE;
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end
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adr_o <= adr_o + 34'd4;
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end
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LOAD_IBUF1:
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LOAD_IBUF1:
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if (ack_i) begin
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if (ack_i|err_i) begin
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case(pc[1:0])
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case(pc[1:0])
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2'd0: ibuf <= dat_i;
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2'd0: ibuf <= dat_i;
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2'd1: ibuf <= dat_i[31:8];
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2'd1: ibuf <= dat_i[31:8];
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2'd2: ibuf <= dat_i[31:16];
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2'd2: ibuf <= dat_i[31:16];
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2'd3: ibuf <= dat_i[31:24];
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2'd3: ibuf <= dat_i[31:24];
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endcase
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endcase
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cstate <= LOAD_IBUF2;
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cstate <= LOAD_IBUF2;
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adr_o <= adr_o + 34'd4;
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adr_o <= adr_o + 34'd4;
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end
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end
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LOAD_IBUF2:
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LOAD_IBUF2:
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if (ack_i) begin
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if (ack_i|err_i) begin
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case(pc[1:0])
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case(pc[1:0])
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2'd0: ibuf[55:32] <= dat_i[23:0];
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2'd0: ibuf[55:32] <= dat_i[23:0];
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2'd1: ibuf[55:24] <= dat_i;
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2'd1: ibuf[55:24] <= dat_i;
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2'd2: ibuf[47:16] <= dat_i;
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2'd2: ibuf[47:16] <= dat_i;
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2'd3: ibuf[39:8] <= dat_i;
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2'd3: ibuf[39:8] <= dat_i;
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| Line 142... |
Line 175... |
adr_o <= 34'd0;
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adr_o <= 34'd0;
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cstate <= IDLE;
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cstate <= IDLE;
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imiss <= `FALSE;
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imiss <= `FALSE;
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bufadr <= pc; // clears the miss
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bufadr <= pc; // clears the miss
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end
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end
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else if (err_i) begin
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case(pc[1:0])
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2'd0: ;
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2'd1: ;
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2'd2: ibuf[55:48] <= dat_i[7:0];
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2'd3: ibuf[55:40] <= dat_i[15:0];
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endcase
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cti_o <= 3'd0;
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bl_o <= 6'd0;
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cyc_o <= 1'b0;
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stb_o <= 1'b0;
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sel_o <= 4'h0;
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adr_o <= 34'd0;
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cstate <= IDLE;
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state <= INSN_BUS_ERROR;
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imiss <= `FALSE;
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bufadr <= pc; // clears the miss
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end
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endcase
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endcase
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