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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [calc.v] - Diff between revs 36 and 38

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Rev 36 Rev 38
Line 36... Line 36...
                `LSR_ZPX,`LSR_ABS,`LSR_ABSX,
                `LSR_ZPX,`LSR_ABS,`LSR_ABSX,
                `ROR_ZPX,`ROR_ABS,`ROR_ABSX,
                `ROR_ZPX,`ROR_ABS,`ROR_ABSX,
                `INC_ZPX,`INC_ABS,`INC_ABSX,
                `INC_ZPX,`INC_ABS,`INC_ABSX,
                `DEC_ZPX,`DEC_ABS,`DEC_ABSX:
                `DEC_ZPX,`DEC_ABS,`DEC_ABSX:
                                state <= STORE1;
                                state <= STORE1;
 
                `SPL_ABS,`SPL_ABSX:
 
                        if (b==32'd0) begin
 
                                pc <= pc - pc_inc2 - 32'd1;
 
                                spi_cnt <= spi_cnt - 8'd1;
 
                                if (spi_cnt==8'd0)
 
                                        spi <= 1'b1;
 
                        end
 
                        else
 
                                spi_cnt <= SPIN_CYCLES;
                endcase
                endcase
        end
        end
endtask
endtask
 
 
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