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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [calc.v] - Diff between revs 10 and 13

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Rev 10 Rev 13
Line 41... Line 41...
                        `CPY_IMM,`CPY_ZP,`CPY_ABS:      begin res8 <= y8 - b8; end
                        `CPY_IMM,`CPY_ZP,`CPY_ABS:      begin res8 <= y8 - b8; end
                        `ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX:    begin res8 <= {b8,1'b0}; wdat <= {4{b8[6:0],1'b0}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX:    begin res8 <= {b8,1'b0}; wdat <= {4{b8[6:0],1'b0}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX:    begin res8 <= {b8,cf}; wdat <= {4{b8[6:0],cf}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX:    begin res8 <= {b8,cf}; wdat <= {4{b8[6:0],cf}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX:    begin res8 <= {b8[0],1'b0,b8[7:1]}; wdat <= {4{1'b0,b8[7:1]}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX:    begin res8 <= {b8[0],1'b0,b8[7:1]}; wdat <= {4{1'b0,b8[7:1]}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX:    begin res8 <= {b8[0],cf,b8[7:1]}; wdat <= {4{cf,b8[7:1]}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX:    begin res8 <= {b8[0],cf,b8[7:1]}; wdat <= {4{cf,b8[7:1]}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX:    begin res8 <= b8 + 1; wdat <= {4{b8+8'd1}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX:    begin res8 <= b8 + 8'd1; wdat <= {4{b8+8'd1}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX:    begin res8 <= b8 - 1; wdat <= {4{b8-8'd1}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        `DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX:    begin res8 <= b8 - 8'd1; wdat <= {4{b8-8'd1}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
                        endcase
                        endcase
                end
                end
                else begin
                else begin
                        case(ir[7:0])
                        case(ir[7:0])
/*                      The following handled in the DECODE stage which reduces the CPI at a cost of clock frequency.
/*                      The following handled in the DECODE stage which reduces the CPI at a cost of clock frequency.

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