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Line 47... |
`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin res8 <= b8 - 8'd1; wdat <= {4{b8-8'd1}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin res8 <= b8 - 8'd1; wdat <= {4{b8-8'd1}}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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endcase
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endcase
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end
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end
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else begin
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else begin
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case(ir[7:0])
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case(ir[7:0])
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/* The following handled in the DECODE stage which reduces the CPI at a cost of clock frequency.
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//The following handled in the DECODE stage which reduces the CPI at a cost of clock frequency.
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`RR:
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`RR:
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case(ir[23:20])
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case(ir[23:20])
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`ADD_RR: res <= a + b;
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// `ADD_RR: res <= a + b;
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`SUB_RR: res <= a - b; // Also CMP
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// `SUB_RR: res <= a - b; // Also CMP
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`AND_RR: res <= a & b; // Also BIT
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// `AND_RR: res <= a & b; // Also BIT
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`OR_RR: res <= a | b;
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// `OR_RR: res <= a | b;
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`EOR_RR: res <= a ^ b;
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// `EOR_RR: res <= a ^ b;
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`MUL_RR: prod <= a * b; // slows the whole core down
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// `MUL_RR: prod <= a * b; // slows the whole core down
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endcase*/
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`ASL_RRR: res <= shlo;
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`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: begin res <= a + b; end
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`LSR_RRR: res <= shro;
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`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: begin res <= a - b; end // Also CMP
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endcase
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`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: begin res <= a & b; end // Also BIT
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`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: begin res <= a + b; end
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`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: begin res <= a | b; end // Also LD
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`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: begin res <= a - b; end // Also CMP
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`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: begin res <= a ^ b; end
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`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: begin res <= a & b; end // Also BIT
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`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: begin res <= a | b; end // Also LD
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`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: begin res <= a ^ b; end
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`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin res <= b; end
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`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin res <= b; end
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`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin res <= b; end
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`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin res <= b; end
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`CPX_IMM32,`CPX_ZPX,`CPX_ABS: begin res <= x - b; end
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`CPX_ZPX,`CPX_ABS: begin res <= x - b; end
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`CPY_IMM32,`CPY_ZPX,`CPY_ABS: begin res <= y - b; end
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`CPY_ZPX,`CPY_ABS: begin res <= y - b; end
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`ASL_RR: begin res <= {a,1'b0}; end
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`ASL_IMM8: res <= shlo;
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`ROL_RR: begin res <= {a,cf}; end
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`LSR_IMM8: res <= shro;
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`LSR_RR: begin res <= {a[0],1'b0,a[31:1]}; end
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//The following handled in the DECODE stage which reduces the CPI at a cost of clock frequency.
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`ROR_RR: begin res <= {a[0],cf,a[31:1]}; end
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// `ASL_RR: begin res <= {a,1'b0}; end
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// `ROL_RR: begin res <= {a,cf}; end
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// `LSR_RR: begin res <= {a[0],1'b0,a[31:1]}; end
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// `ROR_RR: begin res <= {a[0],cf,a[31:1]}; end
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`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin res <= {b,1'b0}; wdat <= {b,1'b0}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin res <= {b,1'b0}; wdat <= {b,1'b0}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin res <= {b,cf}; wdat <= {b,cf}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin res <= {b,cf}; wdat <= {b,cf}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin res <= {b[0],1'b0,b[31:1]}; wdat <= {b[0],1'b0,b[31:1]}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin res <= {b[0],1'b0,b[31:1]}; wdat <= {b[0],1'b0,b[31:1]}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin res <= {b[0],cf,b[31:1]}; wdat <= {b[0],cf,b[31:1]}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin res <= {b[0],cf,b[31:1]}; wdat <= {b[0],cf,b[31:1]}; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`INC_ZPX,`INC_ABS,`INC_ABSX: begin res <= b + 1; wdat <= b + 1; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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`INC_ZPX,`INC_ABS,`INC_ABSX: begin res <= b + 1; wdat <= b + 1; wadr <= radr; wadr2LSB <= radr2LSB; state <= STORE1; end
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