URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [decode.v] - Diff between revs 32 and 35

Rev 32	Rev 35
Line 27...	Line 27...
`state <= IFETCH;`	`state <= IFETCH;`
`pc <= pc + pc_inc;`	`pc <= pc + pc_inc;`
`a <= rfoa;`	`a <= rfoa;`
`res <= alu_out;`	`res <= alu_out;`
`ttrig <= tf;`	`ttrig <= tf;`
	`oisp <= isp; // for bus retry`
`// This case statement should include all opcodes or the opcode`	`// This case statement should include all opcodes or the opcode`
`// will end up being treated as an undefined operation.`	`// will end up being treated as an undefined operation.`
`case(ir9)`	`case(ir9)`
`STP: clk_en <= 1'b0;	`STP: clk_en <= 1'b0;
`NOP: ;	`NOP: ;
Line 101...	Line 102...
`4'h4: ;`	`4'h4: ;`
`4'h5: lfsr <= {lfsr[30:0],lfsr_fb};`	`4'h5: lfsr <= {lfsr[30:0],lfsr_fb};`
`4'd7: ;`	`4'd7: ;`
`4'h8: ;`	`4'h8: ;`
`4'h9: ;`	`4'h9: ;`
	`ifdef DEBUG
`4'hA: history_ndx <= history_ndx + 6'd1;`	`4'hA: history_ndx <= history_ndx + 6'd1;`
	`endif
`4'hE: ;`	`4'hE: ;`
`4'hF: ;`	`4'hF: ;`
`default: ;`	`default: ;`
`endcase`	`endcase`
`end`	`end`
Line 488...	Line 491...
`end`	`end`
`BRK:	`BRK:
`begin`	`begin`
`bf <= !hwi;`	`bf <= !hwi;`
km <= `TRUE;	km <= `TRUE;
	`ifdef DEBUG
hist_capture <= `FALSE;	hist_capture <= `FALSE;
	`endif
`radr <= isp_dec;`	`radr <= isp_dec;`
`wadr <= isp_dec;`	`wadr <= isp_dec;`
`isp <= isp_dec;`	`isp <= isp_dec;`
store_what <= `STW_PCHWI;	store_what <= `STW_PCHWI;
`state <= STORE1;`	`state <= STORE1;`