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URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [decode.v] - Diff between revs 35 and 36

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Rev 35 Rev 36
Line 344... Line 344... 
                        begin
 
                        begin
 
                                wadr <= ir[39:8];
 
                                wadr <= ir[39:8];
 
                                store_what <= `STW_Y;
 
                                store_what <= `STW_Y;
 
                                state <= STORE1;
 
                                state <= STORE1;
 
                        end
 
                        end
 
                `ADD_ZPX,`SUB_ZPX,`AND_ZPX:
 
                `ADD_ZPX,`SUB_ZPX,`AND_ZPX,`TRB_ZPX:
 
                        begin
 
                        begin
 
                                Rt <= ir[19:16];
 
                                Rt <= ir[19:16];
 
                                radr <= zpx32_address;
 
                                radr <= zpx32_address;
 
                                load_what <= `WORD_310;
 
                                load_what <= `WORD_310;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
 
                        end
 
                        end
 
 
 
                `LEA_ZPX:
 
 
 
                        begin
 
 
 
                                Rt <= ir[19:16];
 
 
 
                                res <= zpx32_address;
 
 
 
                                state <= IFETCH;
 
 
 
                        end
 
                // Trim a clock cycle off of loads by testing for Ra = 0.
 
                // Trim a clock cycle off of loads by testing for Ra = 0.
 
                `OR_ZPX,`EOR_ZPX:
 
                `OR_ZPX,`EOR_ZPX,`TSB_ZPX:
 
                        begin
 
                        begin
 
                                Rt <= ir[19:16];
 
                                Rt <= ir[19:16];
 
                                radr <= zpx32_address;
 
                                radr <= zpx32_address;
 
                                load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
 
                                load_what <= (Ra==4'd0) ? `WORD_311: `WORD_310;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
Line 371... Line 377... 
                        begin
 
                        begin
 
                                radr <= zpx32xy_address + acc[31:5];
 
                                radr <= zpx32xy_address + acc[31:5];
 
                                load_what <= `WORD_310;
 
                                load_what <= `WORD_310;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
 
                        end
 
                        end
 
 
 
                `LEA_DSP:
 
 
 
                        begin
 
 
 
                                Rt <= ir[15:12];
 
 
 
                                res <= {{24{ir[23]}},ir[23:16]} + isp;
 
 
 
                                state <= IFETCH;
 
 
 
                        end
 
                `ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
 
                `ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
 
                        begin
 
                        begin
 
                                Rt <= ir[15:12];
 
                                Rt <= ir[15:12];
 
                                radr <= {{24{ir[23]}},ir[23:16]} + isp;
 
                                radr <= {{24{ir[23]}},ir[23:16]} + isp;
 
                                load_what <= `WORD_310;
 
                                load_what <= `WORD_310;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
 
                        end
 
                        end
 
                `ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX:
 
                `ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
 
                        begin
 
                        begin
 
                                if (ir[7:0]!=`ST_IX)     // for ST_IX, Rt=0
 
                                if (ir[7:0]!=`ST_IX)     // for ST_IX, Rt=0
 
                                        Rt <= ir[19:16];
 
                                        Rt <= ir[19:16];
 
                                radr <= zpx32_address;
 
                                radr <= zpx32_address;
 
                                load_what <= `IA_310;
 
                                load_what <= `IA_310;
 
                                store_what <= `STW_A;
 
                                store_what <= `STW_A;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
 
                        end
 
                        end
 
 
 
                `LEA_RIND:
 
 
 
                        begin
 
 
 
                                Rt <= ir[19:16];
 
 
 
                                res <= rfob;
 
 
 
                                state <= IFETCH;
 
 
 
                        end
 
                `ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
 
                `ADD_RIND,`SUB_RIND,`OR_RIND,`AND_RIND,`EOR_RIND:
 
                        begin
 
                        begin
 
                                radr <= rfob;
 
                                radr <= rfob;
 
                                Rt <= ir[19:16];
 
                                Rt <= ir[19:16];
 
                                load_what <= `WORD_310;
 
                                load_what <= `WORD_310;
Line 400... Line 418... 
                        begin
 
                        begin
 
                                wadr <= rfob;
 
                                wadr <= rfob;
 
                                store_what <= `STW_RFA;
 
                                store_what <= `STW_RFA;
 
                                state <= STORE1;
 
                                state <= STORE1;
 
                        end
 
                        end
 
                `ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY:
 
                `ADD_IY,`SUB_IY,`OR_IY,`AND_IY,`EOR_IY,`ST_IY,`LEA_IY:
 
                        begin
 
                        begin
 
                                if (ir[7:0]!=`ST_IY)     // for ST_IY, Rt=0
 
                                if (ir[7:0]!=`ST_IY)     // for ST_IY, Rt=0
 
                                        Rt <= ir[19:16];
 
                                        Rt <= ir[19:16];
 
                                isIY <= 1'b1;
 
                                isIY <= 1'b1;
 
                                radr <= ir[31:20];
 
                                radr <= ir[31:20];
 
                                load_what <= `IA_310;
 
                                load_what <= `IA_310;
 
                                store_what <= `STW_A;
 
                                store_what <= `STW_A;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
 
                        end
 
                        end
 
                `OR_ABS,`EOR_ABS:
 
                `LEA_ABS:
 
 
 
                        begin
 
 
 
                                res <= ir[47:16];
 
 
 
                                Rt <= ir[15:12];
 
 
 
                                state <= IFETCH;
 
 
 
                        end
 
 
 
                `OR_ABS,`EOR_ABS,`TSB_ABS:
 
                        begin
 
                        begin
 
                                radr <= ir[47:16];
 
                                radr <= ir[47:16];
 
                                Rt <= ir[15:12];
 
                                Rt <= ir[15:12];
 
                                load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
 
                                load_what <= (Ra==4'd0) ? `WORD_311 : `WORD_310;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
 
                        end
 
                        end
 
                `ADD_ABS,`SUB_ABS,`AND_ABS:
 
                `ADD_ABS,`SUB_ABS,`AND_ABS,`TRB_ABS:
 
                        begin
 
                        begin
 
                                radr <= ir[47:16];
 
                                radr <= ir[47:16];
 
                                Rt <= ir[15:12];
 
                                Rt <= ir[15:12];
 
                                load_what <= `WORD_310;
 
                                load_what <= `WORD_310;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
Line 436... Line 460... 
                        begin
 
                        begin
 
                                radr <= ir[39:8] + acc[31:5];
 
                                radr <= ir[39:8] + acc[31:5];
 
                                load_what <= `WORD_310;
 
                                load_what <= `WORD_310;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
 
                        end
 
                        end
 
 
 
                `LEA_ABSX:
 
 
 
                        begin
 
 
 
                                res <= absx32_address;
 
 
 
                                Rt <= ir[19:16];
 
 
 
                                state <= IFETCH;
 
 
 
                        end
 
                `ADD_ABSX,`SUB_ABSX,`AND_ABSX:
 
                `ADD_ABSX,`SUB_ABSX,`AND_ABSX:
 
                        begin
 
                        begin
 
                                radr <= absx32_address;
 
                                radr <= absx32_address;
 
                                Rt <= ir[19:16];
 
                                Rt <= ir[19:16];
 
                                load_what <= `WORD_310;
 
                                load_what <= `WORD_310;
Line 668... Line 698... 
                                isp <= isp_dec;
 
                                isp <= isp_dec;
 
                                state <= STORE1;
 
                                state <= STORE1;
 
                        end
 
                        end
 
                `PUSH:
 
                `PUSH:
 
                        begin
 
                        begin
 
 
 
                                if (ir[15:12]==4'h0) begin
 
                                radr <= isp_dec;
 
                                radr <= isp_dec;
 
                                wadr <= isp_dec;
 
                                wadr <= isp_dec;
 
 
 
                                        isp <= isp_dec;
 
 
 
                                end
 
 
 
                                else begin
 
 
 
                                        radr <= rfob-32'd1;
 
 
 
                                        wadr <= rfob-32'd1;
 
 
 
                                        wrrf <= 1'b1;
 
 
 
                                        Rt <= ir[15:12];
 
 
 
                                        res <= rfob-32'd1;
 
 
 
                                end
 
                                store_what <= `STW_A;
 
                                store_what <= `STW_A;
 
                                state <= STORE1;
 
                                state <= STORE1;
 
                                isp <= isp_dec;
 
 
 
                        end
 
                        end
 
                `PUSHA:
 
                `PUSHA:
 
                        begin
 
                        begin
 
                                radr <= isp_dec;
 
                                radr <= isp_dec;
 
                                wadr <= isp_dec;
 
                                wadr <= isp_dec;
Line 716... Line 755... 
                                load_what <= `WORD_311;
 
                                load_what <= `WORD_311;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
 
                        end
 
                        end
 
                `POP:
 
                `POP:
 
                        begin
 
                        begin
 
                                Rt <= ir[15:12];
 
                                if (ir[11:8]!=4'h0) begin
 
 
 
                                        Rt <= ir[11:8];
 
 
 
                                        res <= rfoa+32'd1;
 
 
 
                                        wrrf <= 1'b1;
 
 
 
                                        radr <= rfoa;
 
 
 
                                end
 
 
 
                                else begin
 
                                radr <= isp;
 
                                radr <= isp;
 
                                isp <= isp_inc;
 
                                isp <= isp_inc;
 
 
 
                                end
 
                                load_what <= `WORD_311;
 
                                load_what <= `WORD_311;
 
                                state <= LOAD_MAC1;
 
                                state <= LOAD_MAC1;
 
                        end
 
                        end
 
                `POPA:
 
                `POPA:
 
                        begin
 
                        begin

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