| Line 24... |
Line 24... |
begin
|
begin
|
first_ifetch <= `TRUE;
|
first_ifetch <= `TRUE;
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Rt <= 4'h0; // Default
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Rt <= 4'h0; // Default
|
state <= IFETCH;
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state <= IFETCH;
|
pc <= pc + pc_inc;
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pc <= pc + pc_inc;
|
|
pc_inc2 <= pc_inc;
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a <= rfoa;
|
a <= rfoa;
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res <= alu_out;
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res <= alu_out;
|
ttrig <= tf;
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ttrig <= tf;
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oisp <= isp; // for bus retry
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oisp <= isp; // for bus retry
|
// This case statement should include all opcodes or the opcode
|
// This case statement should include all opcodes or the opcode
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| Line 54... |
Line 55... |
`SEI: im <= 1'b1;
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`SEI: im <= 1'b1;
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`WAI: wai <= 1'b1;
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`WAI: wai <= 1'b1;
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`TON: tf <= 1'b1;
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`TON: tf <= 1'b1;
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`TOFF: tf <= 1'b0;
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`TOFF: tf <= 1'b0;
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`HOFF: hist_capture <= 1'b0;
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`HOFF: hist_capture <= 1'b0;
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`EMM: begin em <= 1'b1;
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// Switching to 65c02 mode zeros out the upper part of the index registers.
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// Switching to 65c816 mode does not zero out the upper part of the index registers,
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// this is unlike switching from '02 to '816 mode. Also, the register size select
|
|
// bits are not affected.
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`XCE: begin
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em <= 1'b1;
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m816 <= ~cf;
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cf <= ~m816;
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if (cf) begin
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x[31:8] <= 24'd0;
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y[31:8] <= 24'd0;
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|
end
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`ifdef SUPPORT_EM8
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`ifdef SUPPORT_EM8
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state <= BYTE_IFETCH;
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next_state(BYTE_IFETCH);
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`endif
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`endif
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end
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end
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`DEX: Rt <= 4'd2;
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`DEX: Rt <= 4'd2;
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// DEX/BNE accelerator
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// DEX/BNE accelerator
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// if (ir[15:8]==`BNE) begin
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// if (ir[15:8]==`BNE) begin
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| Line 155... |
Line 167... |
`ROL_RR: Rt <= ir[15:12];
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`ROL_RR: Rt <= ir[15:12];
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`LSR_RR: Rt <= ir[15:12];
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`LSR_RR: Rt <= ir[15:12];
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`ROR_RR: Rt <= ir[15:12];
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`ROR_RR: Rt <= ir[15:12];
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`DEC_RR: Rt <= ir[15:12];
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`DEC_RR: Rt <= ir[15:12];
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`INC_RR: Rt <= ir[15:12];
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`INC_RR: Rt <= ir[15:12];
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/*
|
|
Can't P&R this
|
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`ADD_R: begin Rt <= ir[11: 8]; b <= rfob; end
|
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`SUB_R: begin Rt <= ir[11: 8]; b <= rfob; end
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`OR_R: begin Rt <= ir[11: 8]; b <= rfob; end
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`AND_R: begin Rt <= ir[11: 8]; b <= rfob; end
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`EOR_R: begin Rt <= ir[11: 8]; b <= rfob; end
|
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*/
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`ADD_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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`SUB_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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`OR_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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`AND_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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`EOR_IMM4: begin Rt <= ir[11: 8]; b <= {{28{ir[15]}},ir[15:12]}; end
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|
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`ADD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
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`ADD_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
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`SUB_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
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`SUB_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; end
|
`MUL_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
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`MUL_IMM8: begin Rt <= ir[15:12]; b <= {{24{ir[23]}},ir[23:16]}; state <= MULDIV1; end
|
`ifdef SUPPORT_DIVMOD
|
`ifdef SUPPORT_DIVMOD
|
| Line 290... |
Line 315... |
store_what <= `STW_RFA8;
|
store_what <= `STW_RFA8;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`ST_DSP:
|
`ST_DSP:
|
begin
|
begin
|
wadr <= {{24{ir[23]}},ir[23:16]} + isp;
|
wadr <= {24'b0,ir[23:16]} + isp;
|
store_what <= `STW_RFA;
|
store_what <= `STW_RFA;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`ST_ABS:
|
`ST_ABS:
|
begin
|
begin
|
| Line 380... |
Line 405... |
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`LEA_DSP:
|
`LEA_DSP:
|
begin
|
begin
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
res <= {{24{ir[23]}},ir[23:16]} + isp;
|
res <= {24'b0,ir[23:16]} + isp;
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
|
`ADD_DSP,`SUB_DSP,`OR_DSP,`AND_DSP,`EOR_DSP:
|
begin
|
begin
|
Rt <= ir[15:12];
|
Rt <= ir[15:12];
|
radr <= {{24{ir[23]}},ir[23:16]} + isp;
|
radr <= {24'b0,ir[23:16]} + isp;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
|
`ADD_IX,`SUB_IX,`OR_IX,`AND_IX,`EOR_IX,`ST_IX,`LEA_IX:
|
begin
|
begin
|
| Line 454... |
Line 479... |
begin
|
begin
|
radr <= ir[39:8];
|
radr <= ir[39:8];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
`SPL_ABS:
|
|
begin
|
|
Rt <= 4'h0;
|
|
radr <= ir[39:8];
|
|
load_what <= `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
|
`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS:
|
begin
|
begin
|
radr <= ir[39:8] + acc[31:5];
|
radr <= ir[39:8] + acc[31:5];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
| Line 492... |
Line 524... |
begin
|
begin
|
radr <= absx32xy_address + acc[31:5];
|
radr <= absx32xy_address + acc[31:5];
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
|
`SPL_ABSX:
|
|
begin
|
|
Rt <= 4'h0;
|
|
radr <= absx32xy_address;
|
|
load_what <= `WORD_310;
|
|
state <= LOAD_MAC1;
|
|
end
|
|
|
`CPX_ZPX:
|
`CPX_ZPX:
|
begin
|
begin
|
radr <= zpx32xy_address;
|
radr <= zpx32xy_address;
|
load_what <= `WORD_310;
|
load_what <= `WORD_310;
|
| Line 534... |
Line 573... |
end
|
end
|
`INT0,`INT1:
|
`INT0,`INT1:
|
begin
|
begin
|
pg2 <= `FALSE;
|
pg2 <= `FALSE;
|
ir <= {8{`BRK}};
|
ir <= {8{`BRK}};
|
vect <= {vbr[31:9],ir[15:7],2'b00};
|
vect <= {vbr[31:9],ir[0],ir[15:8],2'b00};
|
state <= DECODE;
|
state <= DECODE;
|
end
|
end
|
`JMP:
|
`JMP:
|
begin
|
begin
|
pc[15:0] <= ir[23:8];
|
pc[15:0] <= ir[23:8];
|
| Line 781... |
Line 820... |
`ifdef SUPPORT_STRING
|
`ifdef SUPPORT_STRING
|
`MVN:
|
`MVN:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= x;
|
radr <= x;
|
res <= x + 32'd1;
|
res <= x_inc;
|
load_what <= `WORD_312;
|
load_what <= `WORD_312;
|
|
pc <= pc;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`MVP:
|
`MVP:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= x;
|
radr <= x;
|
res <= x - 32'd1;
|
res <= x_dec;
|
load_what <= `WORD_312;
|
load_what <= `WORD_312;
|
|
pc <= pc;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`STS:
|
`STS:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= y;
|
radr <= y;
|
wadr <= y;
|
wadr <= y;
|
store_what <= `STW_X;
|
store_what <= `STW_X;
|
acc <= acc - 32'd1;
|
acc <= acc_dec;
|
|
pc <= pc;
|
state <= STORE1;
|
state <= STORE1;
|
end
|
end
|
`CMPS:
|
`CMPS:
|
begin
|
begin
|
Rt <= 4'd3;
|
Rt <= 4'd3;
|
radr <= x;
|
radr <= x;
|
res <= x + 32'd1;
|
res <= x_inc;
|
|
pc <= pc;
|
load_what <= `WORD_313;
|
load_what <= `WORD_313;
|
state <= LOAD_MAC1;
|
state <= LOAD_MAC1;
|
end
|
end
|
`endif
|
`endif
|
`PG2: begin
|
`PG2: begin
|
