| Line 20... |
Line 20... |
//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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IFETCH:
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IFETCH:
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begin
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begin
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ic_whence <= IFETCH;
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vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
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vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
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suppress_pcinc <= 4'hF; // default: no suppression of increment
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suppress_pcinc <= 4'hF; // default: no suppression of increment
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opc <= pc;
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opc <= pc;
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hwi <= `FALSE;
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hwi <= `FALSE;
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isBusErr <= `FALSE;
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isBusErr <= `FALSE;
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pg2 <= `FALSE;
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pg2 <= `FALSE;
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isIY <= `FALSE;
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isIY24 <= `FALSE;
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store_what <= `STW_DEF;
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store_what <= `STW_DEF;
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if (nmi_edge & gie & !isExec & !isAtni) begin
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if (nmi_edge & gie & !isExec & !isAtni) begin
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ir[7:0] <= `BRK;
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ir[7:0] <= `BRK;
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nmi_edge <= 1'b0;
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nmi_edge <= 1'b0;
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wai <= 1'b0;
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wai <= 1'b0;
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hwi <= `TRUE;
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hwi <= `TRUE;
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next_state(DECODE);
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next_state(DECODE);
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vect <= `NMI_VECT;
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vect <= `NMI_VECT;
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end
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end
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else if (irq_i & gie & !isExec & !isAtni) begin
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else if ((irq_i|spi) & gie & !isExec & !isAtni) begin
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wai <= 1'b0;
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wai <= 1'b0;
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if (im) begin
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if (im) begin
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if (ttrig) begin
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if (ttrig) begin
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ir[7:0] <= `BRK;
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ir[7:0] <= `BRK;
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vect <= {vbr[31:9],9'd490,2'b00};
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vect <= {vbr[31:9],9'd490,2'b00};
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| Line 68... |
Line 71... |
exbuf <= 64'd0;
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exbuf <= 64'd0;
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next_state(DECODE);
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next_state(DECODE);
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end
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end
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else begin
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else begin
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pg2 <= pg2;
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pg2 <= pg2;
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state <= ICACHE1;
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next_state(ICACHE1);
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end
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end
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end
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end
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end
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end
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else begin
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else begin
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ir[7:0] <= `BRK;
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ir[7:0] <= `BRK;
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hwi <= `TRUE;
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hwi <= `TRUE;
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if (spi) begin
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spi <= 1'b0;
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spi_cnt <= SPIN_CYCLES;
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vect <= {vbr[31:9],9'd3,2'b00};
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end
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else begin
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vect <= {vbr[31:9],irq_vect,2'b00};
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vect <= {vbr[31:9],irq_vect,2'b00};
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end
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next_state(DECODE);
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next_state(DECODE);
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end
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end
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end
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end
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else if (!wai) begin
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else if (!wai) begin
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if (ttrig) begin
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if (ttrig) begin
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| Line 142... |
Line 152... |
`endif
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`endif
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end
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end
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4'h5: lfsr <= res[31:0];
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4'h5: lfsr <= res[31:0];
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4'h7: abs8 <= res[31:0];
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4'h7: abs8 <= res[31:0];
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4'h8: begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
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4'h8: begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
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4'hE: begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end
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4'hE: begin sp <= res[15:0]; spage[31:16] <= res[31:16]; end
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4'hF: begin isp <= res[31:0]; gie <= 1'b1; end
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4'hF: begin isp <= res[31:0]; gie <= 1'b1; end
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endcase
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endcase
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end
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end
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`RR:
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`RR:
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case(ir[23:20])
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case(ir[23:20])
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| Line 164... |
Line 174... |
default:
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default:
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begin nf <= resn32; zf <= resz32; end
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begin nf <= resn32; zf <= resz32; end
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endcase
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endcase
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`LD_RR: begin zf <= resz32; nf <= resn32; end
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`LD_RR: begin zf <= resz32; nf <= resn32; end
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`DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
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`DEC_RR,`INC_RR: begin zf <= resz32; nf <= resn32; end
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`ADD_IMM4,`ADD_R,
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`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
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`ADD_IMM8,`ADD_IMM16,`ADD_IMM32,`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND:
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begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
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begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
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`SUB_IMM4,`SUB_R,
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`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
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`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
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if (Rt==4'h0) // CMP doesn't set overflow
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if (Rt==4'h0) // CMP doesn't set overflow
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begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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else
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else
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begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
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begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
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| Line 177... |
Line 189... |
`DIV_IMM8,`DIV_IMM16,`DIV_IMM32,
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`DIV_IMM8,`DIV_IMM16,`DIV_IMM32,
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`MOD_IMM8,`MOD_IMM16,`MOD_IMM32,
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`MOD_IMM8,`MOD_IMM16,`MOD_IMM32,
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`endif
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`endif
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`MUL_IMM8,`MUL_IMM16,`MUL_IMM32:
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`MUL_IMM8,`MUL_IMM16,`MUL_IMM32:
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begin nf <= resn32; zf <= resz32; end
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begin nf <= resn32; zf <= resz32; end
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`AND_IMM4,`AND_R,
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`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
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`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
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if (Rt==4'h0) // BIT sets overflow
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if (Rt==4'h0) // BIT sets overflow
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begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
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begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
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else
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else
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begin nf <= resn32; zf <= resz32; end
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begin nf <= resn32; zf <= resz32; end
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`ORB_ZPX,`ORB_ABS,`ORB_ABSX,
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`ORB_ZPX,`ORB_ABS,`ORB_ABSX,
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`OR_IMM4,`OR_R,
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`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
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`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
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`EOR_IMM4,`EOR_R,
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`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
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`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
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begin nf <= resn32; zf <= resz32; end
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begin nf <= resn32; zf <= resz32; end
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`ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
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`ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
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begin cf <= resc32; nf <= resn32; zf <= resz32; end
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begin cf <= resc32; nf <= resn32; zf <= resz32; end
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`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
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`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
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| Line 215... |
Line 230... |
`POP: begin nf <= resn32; zf <= resz32; end
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`POP: begin nf <= resn32; zf <= resz32; end
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`TRB_ZPX,`TRB_ABS,`TSB_ZPX,`TSB_ABS:
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`TRB_ZPX,`TRB_ABS,`TSB_ZPX,`TSB_ABS:
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begin zf <= resz32; end
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begin zf <= resz32; end
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`BMT_ZPX,`BMT_ABS,`BMT_ABSX:
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`BMT_ZPX,`BMT_ABS,`BMT_ABSX:
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begin zf <= resz32; nf <= resn32; end
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begin zf <= resz32; nf <= resn32; end
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// `SPL: begin if (radr==65002) acc <= 32'h52544600; end
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endcase
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endcase
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end
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end
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No newline at end of file
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No newline at end of file
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