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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
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//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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IFETCH:
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IFETCH:
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begin
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begin
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opc <= pc;
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if (nmi_edge & !imiss & gie) begin // imiss indicates cache controller is active and this state is in a waiting loop
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if (nmi_edge & !imiss & gie) begin // imiss indicates cache controller is active and this state is in a waiting loop
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nmi_edge <= 1'b0;
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nmi_edge <= 1'b0;
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wai <= 1'b0;
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wai <= 1'b0;
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bf <= 1'b0;
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bf <= 1'b0;
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if (em & !nmoi) begin
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if (em & !nmoi) begin
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Line 218... |
Line 219... |
default: ;
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default: ;
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endcase
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endcase
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case(ir[7:0])
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case(ir[7:0])
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`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
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`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
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`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
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`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
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`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
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`TAS,`TXS,`SUB_SP: begin isp <= res; gie <= 1'b1; end
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`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
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`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
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`TRS:
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`TRS:
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begin
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begin
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case(ir[15:12])
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case(ir[15:12])
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4'h0: begin
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4'h0: begin
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