| Line 20... |
Line 20... |
//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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IFETCH:
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IFETCH:
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begin
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begin
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suppress_pcinc <= 4'hF; // default: no suppression of increment
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opc <= pc;
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opc <= pc;
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if (nmi_edge & !imiss & gie) begin // imiss indicates cache controller is active and this state is in a waiting loop
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hwi <= `FALSE;
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if (nmi_edge & !imiss & gie & !isExec & !isAtni) begin // imiss indicates cache controller is active and this state is in a waiting loop
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nmi_edge <= 1'b0;
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nmi_edge <= 1'b0;
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wai <= 1'b0;
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wai <= 1'b0;
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bf <= 1'b0;
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bf <= 1'b0;
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hwi <= `TRUE;
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if (em & !nmoi) begin
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if (em & !nmoi) begin
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radr <= {spage[31:8],sp[7:2]};
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radr <= {spage[31:8],sp[7:2]};
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radr2LSB <= sp[1:0];
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radr2LSB <= sp[1:0];
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wadr <= {spage[31:8],sp[7:2]};
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wadr <= {spage[31:8],sp[7:2]};
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wadr2LSB <= sp[1:0];
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wadr2LSB <= sp[1:0];
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| Line 60... |
Line 63... |
dat_o <= pc;
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dat_o <= pc;
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vect <= `NMI_VECT;
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vect <= `NMI_VECT;
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state <= IRQ1;
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state <= IRQ1;
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end
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end
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end
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end
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else if (irq_i && !imiss & gie) begin
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else if (irq_i && !imiss & gie & !isExec & !isAtni) begin
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if (im) begin
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if (im) begin
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wai <= 1'b0;
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wai <= 1'b0;
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if (unCachedInsn) begin
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if (isExec) begin
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ir <= exbuf;
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exbuf <= 64'd0;
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suppress_pcinc <= 4'h0;
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state <= em ? BYTE_DECODE : DECODE;
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end
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else if (unCachedInsn) begin
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if (bhit) begin
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if (bhit) begin
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ir <= ibuf;
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ir <= ibuf + exbuf;
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exbuf <= 64'd0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= em ? BYTE_DECODE : DECODE;
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end
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end
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else
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else
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imiss <= `TRUE;
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imiss <= `TRUE;
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end
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end
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else begin
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else begin
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if (ihit) begin
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if (ihit) begin
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ir <= insn;
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ir <= insn + exbuf;
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exbuf <= 64'd0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= em ? BYTE_DECODE : DECODE;
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end
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end
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else
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else
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imiss <= `TRUE;
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imiss <= `TRUE;
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end
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end
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end
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end
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else begin
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else begin
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bf <= 1'b0;
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bf <= 1'b0;
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wai <= 1'b0;
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wai <= 1'b0;
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hwi <= `TRUE;
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if (em & !nmoi) begin
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if (em & !nmoi) begin
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radr <= {spage[31:8],sp[7:2]};
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radr <= {spage[31:8],sp[7:2]};
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radr2LSB <= sp[1:0];
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radr2LSB <= sp[1:0];
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wadr <= {spage[31:8],sp[7:2]};
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wadr <= {spage[31:8],sp[7:2]};
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wadr2LSB <= sp[1:0];
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wadr2LSB <= sp[1:0];
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| Line 120... |
Line 132... |
state <= IRQ1;
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state <= IRQ1;
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end
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end
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end
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end
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end
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end
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else if (!wai) begin
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else if (!wai) begin
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if (unCachedInsn) begin
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if (isExec) begin
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ir <= exbuf;
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exbuf <= 64'd0;
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suppress_pcinc <= 4'h0;
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state <= em ? BYTE_DECODE : DECODE;
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end
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else if (unCachedInsn) begin
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if (bhit) begin
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if (bhit) begin
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ir <= ibuf;
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ir <= ibuf + exbuf;
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exbuf <= 64'd0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= em ? BYTE_DECODE : DECODE;
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end
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end
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else
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else
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imiss <= `TRUE;
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imiss <= `TRUE;
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end
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end
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else begin
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else begin
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if (ihit) begin
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if (ihit) begin
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ir <= insn;
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ir <= insn + exbuf;
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exbuf <= 64'd0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= em ? BYTE_DECODE : DECODE;
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end
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end
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else
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else
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imiss <= `TRUE;
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imiss <= `TRUE;
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end
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end
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| Line 219... |
Line 239... |
default: ;
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default: ;
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endcase
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endcase
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case(ir[7:0])
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case(ir[7:0])
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`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
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`TAY,`TXY,`DEY,`INY: begin y <= res; nf <= resn32; zf <= resz32; end
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`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
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`TAX,`TYX,`TSX,`DEX,`INX: begin x <= res; nf <= resn32; zf <= resz32; end
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`TAS,`TXS,`SUB_SP: begin isp <= res; gie <= 1'b1; end
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`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
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`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res;
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`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
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`TSA,`TYA,`TXA,`INA,`DEA: begin acc <= res; nf <= resn32; zf <= resz32; end
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`TRS:
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`TRS:
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begin
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begin
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case(ir[15:12])
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case(ir[15:12])
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4'h0: begin
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4'h0: begin
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