| Line 20... |
Line 20... |
//
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//
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// ============================================================================
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// ============================================================================
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//
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//
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IFETCH:
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IFETCH:
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begin
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begin
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if (em)
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vect <= `BYTE_IRQ_VECT;
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else
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vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
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vect <= {vbr[31:9],`BRK_VECTNO,2'b00};
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suppress_pcinc <= 4'hF; // default: no suppression of increment
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suppress_pcinc <= 4'hF; // default: no suppression of increment
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opc <= pc;
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opc <= pc;
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hwi <= `FALSE;
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hwi <= `FALSE;
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isBusErr <= `FALSE;
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pg2 <= `FALSE;
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store_what <= `STW_DEF;
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store_what <= `STW_DEF;
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if (nmi_edge & !imiss & gie & !isExec & !isAtni) begin // imiss indicates cache controller is active and this state is in a waiting loop
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if (nmi_edge & gie & !isExec & !isAtni) begin // imiss indicates cache controller is active and this state is in a waiting loop
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ir <= 64'd0;
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ir[7:0] <= `BRK;
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nmi_edge <= 1'b0;
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nmi_edge <= 1'b0;
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wai <= 1'b0;
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wai <= 1'b0;
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hwi <= `TRUE;
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hwi <= `TRUE;
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if (em & !nmoi) begin
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vect <= `BYTE_NMI_VECT;
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state <= BYTE_DECODE;
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end
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else begin
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state <= DECODE;
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state <= DECODE;
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vect <= `NMI_VECT;
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vect <= `NMI_VECT;
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end
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end
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end
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else if (irq_i & gie & !isExec & !isAtni) begin
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else if (irq_i && !imiss & gie & !isExec & !isAtni) begin
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wai <= 1'b0;
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wai <= 1'b0;
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if (im) begin
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if (im) begin
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if (isExec) begin
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if (ttrig) begin
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ir[7:0] <= `BRK;
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vect <= {vbr[31:9],9'd490,2'b00};
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state <= DECODE;
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end
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else if (isExec) begin
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ir <= exbuf;
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ir <= exbuf;
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exbuf <= 64'd0;
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exbuf <= 64'd0;
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suppress_pcinc <= 4'h0;
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suppress_pcinc <= 4'h0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= DECODE;
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end
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end
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else if (unCachedInsn) begin
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else if (unCachedInsn) begin
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if (bhit) begin
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if (bhit) begin
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ir <= ibuf + exbuf;
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ir <= ibuf + exbuf;
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exbuf <= 64'd0;
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exbuf <= 64'd0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= DECODE;
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end
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end
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else
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else
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imiss <= `TRUE;
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state <= LOAD_IBUF1;
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end
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end
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else begin
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else begin
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if (ihit) begin
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if (ihit) begin
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ir <= insn + exbuf;
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ir <= insn + exbuf;
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exbuf <= 64'd0;
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exbuf <= 64'd0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= DECODE;
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end
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end
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else
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else
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imiss <= `TRUE;
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state <= ICACHE1;
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end
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end
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end
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end
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else begin
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else begin
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ir <= 64'd0;
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ir[7:0] <= `BRK;
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hwi <= `TRUE;
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hwi <= `TRUE;
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if (em & !nmoi) begin
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state <= BYTE_DECODE;
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end
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else begin
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vect <= {vbr[31:9],irq_vect,2'b00};
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vect <= {vbr[31:9],irq_vect,2'b00};
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state <= DECODE;
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state <= DECODE;
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end
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end
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end
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end
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end
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else if (!wai) begin
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else if (!wai) begin
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if (isExec) begin
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if (ttrig) begin
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ir[7:0] <= `BRK;
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vect <= {vbr[31:9],9'd490,2'b00};
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state <= DECODE;
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end
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else if (isExec) begin
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ir <= exbuf;
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ir <= exbuf;
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exbuf <= 64'd0;
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exbuf <= 64'd0;
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suppress_pcinc <= 4'h0;
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suppress_pcinc <= 4'h0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= DECODE;
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end
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end
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else if (unCachedInsn) begin
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else if (unCachedInsn) begin
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if (bhit) begin
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if (bhit) begin
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ir <= ibuf + exbuf;
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ir <= ibuf + exbuf;
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exbuf <= 64'd0;
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exbuf <= 64'd0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= DECODE;
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end
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end
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else
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else
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imiss <= `TRUE;
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state <= LOAD_IBUF1;
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end
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end
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else begin
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else begin
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if (ihit) begin
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if (ihit) begin
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ir <= insn + exbuf;
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ir <= insn + exbuf;
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exbuf <= 64'd0;
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exbuf <= 64'd0;
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state <= em ? BYTE_DECODE : DECODE;
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state <= DECODE;
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end
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end
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else
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else
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imiss <= `TRUE;
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state <= ICACHE1;
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end
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end
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end
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end
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if (first_ifetch) begin
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// During a cache miss all these assignments will repeat. It's not a
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first_ifetch <= `FALSE;
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// problem. The history buffer will be stuffed with the same pc address
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// for several cycles until the cache load is complete.
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if (hist_capture) begin
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if (hist_capture) begin
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history_buf[history_ndx] <= pc;
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history_buf[history_ndx] <= pc;
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history_ndx <= history_ndx+6'd1;
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history_ndx <= history_ndx+7'd1;
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end
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`ifdef SUPPORT_EM8
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if (em) begin
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case(ir[7:0])
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`TAY,`TXY,`DEY,`INY: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`TAX,`TYX,`TSX,`DEX,`INX: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`TSA,`TYA,`TXA,`INA,`DEA: begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`TAS,`TXS: begin sp <= res8[7:0]; end
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`ADC_IMM:
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begin
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acc[7:0] <= df ? bcaio : res8;
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cf <= df ? bcaico : resc8;
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// vf <= resv8;
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vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
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nf <= df ? bcaio[7] : resn8;
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zf <= df ? bcaio==8'h00 : resz8;
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end
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`ADC_ZP,`ADC_ZPX,`ADC_IX,`ADC_IY,`ADC_ABS,`ADC_ABSX,`ADC_ABSY,`ADC_I:
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begin
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acc[7:0] <= df ? bcao : res8;
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cf <= df ? bcaco : resc8;
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vf <= (res8[7] ^ b8[7]) & (1'b1 ^ acc[7] ^ b8[7]);
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nf <= df ? bcao[7] : resn8;
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zf <= df ? bcao==8'h00 : resz8;
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end
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`SBC_IMM:
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begin
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acc[7:0] <= df ? bcsio : res8;
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cf <= ~(df ? bcsico : resc8);
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vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
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nf <= df ? bcsio[7] : resn8;
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zf <= df ? bcsio==8'h00 : resz8;
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end
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end
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`SBC_ZP,`SBC_ZPX,`SBC_IX,`SBC_IY,`SBC_ABS,`SBC_ABSX,`SBC_ABSY,`SBC_I:
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begin
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acc[7:0] <= df ? bcso : res8;
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vf <= (1'b1 ^ res8[7] ^ b8[7]) & (acc[7] ^ b8[7]);
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cf <= ~(df ? bcsco : resc8);
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nf <= df ? bcso[7] : resn8;
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zf <= df ? bcso==8'h00 : resz8;
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end
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`CMP_IMM,`CMP_ZP,`CMP_ZPX,`CMP_IX,`CMP_IY,`CMP_ABS,`CMP_ABSX,`CMP_ABSY,`CMP_I,
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`CPX_IMM,`CPX_ZP,`CPX_ABS,
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`CPY_IMM,`CPY_ZP,`CPY_ABS:
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begin cf <= ~resc8; nf <= resn8; zf <= resz8; end
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`BIT_IMM,`BIT_ZP,`BIT_ZPX,`BIT_ABS,`BIT_ABSX:
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begin nf <= b8[7]; vf <= b8[6]; zf <= resz8; end
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`TRB_ZP,`TRB_ABS,`TSB_ZP,`TSB_ABS:
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begin zf <= resz8; end
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`LDA_IMM,`LDA_ZP,`LDA_ZPX,`LDA_IX,`LDA_IY,`LDA_ABS,`LDA_ABSX,`LDA_ABSY,`LDA_I,
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`AND_IMM,`AND_ZP,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_ABSY,`AND_I,
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`ORA_IMM,`ORA_ZP,`ORA_ZPX,`ORA_IX,`ORA_IY,`ORA_ABS,`ORA_ABSX,`ORA_ABSY,`ORA_I,
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`EOR_IMM,`EOR_ZP,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_ABSY,`EOR_I:
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begin acc[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`ASL_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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`ROL_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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`LSR_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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`ROR_ACC: begin acc[7:0] <= res8; cf <= resc8; nf <= resn8; zf <= resz8; end
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`ASL_ZP,`ASL_ZPX,`ASL_ABS,`ASL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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`ROL_ZP,`ROL_ZPX,`ROL_ABS,`ROL_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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`LSR_ZP,`LSR_ZPX,`LSR_ABS,`LSR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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`ROR_ZP,`ROR_ZPX,`ROR_ABS,`ROR_ABSX: begin cf <= resc8; nf <= resn8; zf <= resz8; end
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`INC_ZP,`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn8; zf <= resz8; end
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`DEC_ZP,`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn8; zf <= resz8; end
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`PLA: begin acc[7:0] <= res8; zf <= resz8; nf <= resn8; end
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`PLX: begin x[7:0] <= res8; zf <= resz8; nf <= resn8; end
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`PLY: begin y[7:0] <= res8; zf <= resz8; nf <= resn8; end
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`LDX_IMM,`LDX_ZP,`LDX_ZPY,`LDX_ABS,`LDX_ABSY: begin x[7:0] <= res8; nf <= resn8; zf <= resz8; end
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`LDY_IMM,`LDY_ZP,`LDY_ZPX,`LDY_ABS,`LDY_ABSX: begin y[7:0] <= res8; nf <= resn8; zf <= resz8; end
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endcase
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end
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else
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`endif
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begin
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regfile[Rt] <= res;
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regfile[Rt] <= res;
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case(Rt)
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case(Rt)
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4'h1: acc <= res;
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4'h1: acc <= res;
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4'h2: x <= res;
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4'h2: x <= res;
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4'h3: y <= res;
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4'h3: y <= res;
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default: ;
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default: ;
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endcase
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endcase
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case(ir[7:0])
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case(ir9)
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`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
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`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
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`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res;
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`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res;
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`TRS:
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`TRS:
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begin
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begin
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case(ir[15:12])
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case(ir[15:12])
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| Line 242... |
Line 168... |
`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
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`SUB_IMM8,`SUB_IMM16,`SUB_IMM32,`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND:
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if (Rt==4'h0) // CMP doesn't set overflow
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if (Rt==4'h0) // CMP doesn't set overflow
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begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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else
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else
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begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
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begin vf <= resv32; cf <= ~resc32; nf <= resn32; zf <= resz32; end
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`ifdef SUPPORT_DIVMOD
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`DIV_IMM8,`DIV_IMM16,`DIV_IMM32,
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`MOD_IMM8,`MOD_IMM16,`MOD_IMM32,
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`endif
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`MUL_IMM8,`MUL_IMM16,`MUL_IMM32:
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begin nf <= resn32; zf <= resz32; end
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`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
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`AND_IMM8,`AND_IMM16,`AND_IMM32,`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND:
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if (Rt==4'h0) // BIT sets overflow
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if (Rt==4'h0) // BIT sets overflow
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begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
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begin nf <= b[31]; vf <= b[30]; zf <= resz32; end
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else
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else
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begin nf <= resn32; zf <= resz32; end
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begin nf <= resn32; zf <= resz32; end
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`ORB_ZPX,`ORB_ABS,`ORB_ABSX,
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`ORB_ZPX,`ORB_ABS,`ORB_ABSX,
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`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
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`OR_IMM8,`OR_IMM16,`OR_IMM32,`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,
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`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
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`EOR_IMM8,`EOR_IMM16,`EOR_IMM32,`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND:
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begin nf <= resn32; zf <= resz32; end
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begin nf <= resn32; zf <= resz32; end
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`ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
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`ASL_ACC,`ROL_ACC,`LSR_ACC,`ROR_ACC:
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begin acc <= res; cf <= resc32; nf <= resn32; zf <= resz32; end
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begin cf <= resc32; nf <= resn32; zf <= resz32; end
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`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
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`ASL_RR,`ROL_RR,`LSR_RR,`ROR_RR,
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`ASL_ZPX,`ASL_ABS,`ASL_ABSX,
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`ASL_ZPX,`ASL_ABS,`ASL_ABSX,
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`ROL_ZPX,`ROL_ABS,`ROL_ABSX,
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`ROL_ZPX,`ROL_ABS,`ROL_ABSX,
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`LSR_ZPX,`LSR_ABS,`LSR_ABSX,
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`LSR_ZPX,`LSR_ABS,`LSR_ABSX,
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`ROR_ZPX,`ROR_ABS,`ROR_ABSX:
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`ROR_ZPX,`ROR_ABS,`ROR_ABSX:
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begin cf <= resc32; nf <= resn32; zf <= resz32; end
|
begin cf <= resc32; nf <= resn32; zf <= resz32; end
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`ASL_IMM8: begin nf <= resn32; zf <= resz32; end
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`ASL_IMM8: begin nf <= resn32; zf <= resz32; end
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`LSR_IMM8: begin nf <= resn32; zf <= resz32; end
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`LSR_IMM8: begin nf <= resn32; zf <= resz32; end
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`BMT_ZPX,`BMT_ABS,`BMT_ABSX: begin nf <= resn32; zf <= resz32; end
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`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
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`INC_ZPX,`INC_ABS,`INC_ABSX: begin nf <= resn32; zf <= resz32; end
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`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
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`DEC_ZPX,`DEC_ABS,`DEC_ABSX: begin nf <= resn32; zf <= resz32; end
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`TAX,`TYX,`TSX,`DEX,`INX,
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`TAX,`TYX,`TSX,`DEX,`INX,
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`LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`PLX:
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`LDX_IMM32,`LDX_IMM16,`LDX_IMM8,`LDX_ZPY,`LDX_ABS,`LDX_ABSY,`PLX:
|
begin x <= res; nf <= resn32; zf <= resz32; end
|
begin nf <= resn32; zf <= resz32; end
|
`TAY,`TXY,`DEY,`INY,
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`TAY,`TXY,`DEY,`INY,
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`LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`PLY:
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`LDY_IMM32,`LDY_ZPX,`LDY_ABS,`LDY_ABSX,`PLY:
|
begin y <= res; nf <= resn32; zf <= resz32; end
|
begin nf <= resn32; zf <= resz32; end
|
`CPX_IMM32,`CPX_ZPX,`CPX_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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`CPX_IMM32,`CPX_ZPX,`CPX_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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`CPY_IMM32,`CPY_ZPX,`CPY_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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`CPY_IMM32,`CPY_ZPX,`CPY_ABS: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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`CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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`CMP_IMM8: begin cf <= ~resc32; nf <= resn32; zf <= resz32; end
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`TSA,`TYA,`TXA,`INA,`DEA,
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`TSA,`TYA,`TXA,`INA,`DEA,
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`LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA: begin acc <= res; nf <= resn32; zf <= resz32; end
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`LDA_IMM32,`LDA_IMM16,`LDA_IMM8,`PLA: begin nf <= resn32; zf <= resz32; end
|
`POP: begin nf <= resn32; zf <= resz32; end
|
`POP: begin nf <= resn32; zf <= resz32; end
|
endcase
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endcase
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end
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end
|
end
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end
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