| Line 27... |
Line 27... |
opc <= pc;
|
opc <= pc;
|
hwi <= `FALSE;
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hwi <= `FALSE;
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isBusErr <= `FALSE;
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isBusErr <= `FALSE;
|
pg2 <= `FALSE;
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pg2 <= `FALSE;
|
store_what <= `STW_DEF;
|
store_what <= `STW_DEF;
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if (nmi_edge & gie & !isExec & !isAtni) begin // imiss indicates cache controller is active and this state is in a waiting loop
|
if (nmi_edge & gie & !isExec & !isAtni) begin
|
ir[7:0] <= `BRK;
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ir[7:0] <= `BRK;
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nmi_edge <= 1'b0;
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nmi_edge <= 1'b0;
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wai <= 1'b0;
|
wai <= 1'b0;
|
hwi <= `TRUE;
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hwi <= `TRUE;
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state <= DECODE;
|
next_state(DECODE);
|
vect <= `NMI_VECT;
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vect <= `NMI_VECT;
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end
|
end
|
else if (irq_i & gie & !isExec & !isAtni) begin
|
else if (irq_i & gie & !isExec & !isAtni) begin
|
wai <= 1'b0;
|
wai <= 1'b0;
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if (im) begin
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if (im) begin
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if (ttrig) begin
|
if (ttrig) begin
|
ir[7:0] <= `BRK;
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ir[7:0] <= `BRK;
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vect <= {vbr[31:9],9'd490,2'b00};
|
vect <= {vbr[31:9],9'd490,2'b00};
|
state <= DECODE;
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next_state(DECODE);
|
end
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end
|
else if (isExec) begin
|
else if (isExec) begin
|
ir <= exbuf;
|
ir <= exbuf;
|
exbuf <= 64'd0;
|
exbuf <= 64'd0;
|
suppress_pcinc <= 4'h0;
|
suppress_pcinc <= 4'h0;
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state <= DECODE;
|
next_state(DECODE);
|
end
|
end
|
else if (unCachedInsn) begin
|
else if (unCachedInsn) begin
|
if (bhit) begin
|
if (bhit) begin
|
ir <= ibuf + exbuf;
|
ir <= ibuf + exbuf;
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exbuf <= 64'd0;
|
exbuf <= 64'd0;
|
state <= DECODE;
|
next_state(DECODE);
|
end
|
end
|
else
|
else begin
|
|
pg2 <= pg2;
|
state <= LOAD_IBUF1;
|
state <= LOAD_IBUF1;
|
end
|
end
|
|
end
|
else begin
|
else begin
|
if (ihit) begin
|
if (ihit) begin
|
ir <= insn + exbuf;
|
ir <= insn + exbuf;
|
exbuf <= 64'd0;
|
exbuf <= 64'd0;
|
state <= DECODE;
|
next_state(DECODE);
|
end
|
end
|
else
|
else begin
|
|
pg2 <= pg2;
|
state <= ICACHE1;
|
state <= ICACHE1;
|
end
|
end
|
end
|
end
|
|
end
|
else begin
|
else begin
|
ir[7:0] <= `BRK;
|
ir[7:0] <= `BRK;
|
hwi <= `TRUE;
|
hwi <= `TRUE;
|
vect <= {vbr[31:9],irq_vect,2'b00};
|
vect <= {vbr[31:9],irq_vect,2'b00};
|
state <= DECODE;
|
next_state(DECODE);
|
end
|
end
|
end
|
end
|
else if (!wai) begin
|
else if (!wai) begin
|
if (ttrig) begin
|
if (ttrig) begin
|
ir[7:0] <= `BRK;
|
ir[7:0] <= `BRK;
|
vect <= {vbr[31:9],9'd490,2'b00};
|
vect <= {vbr[31:9],9'd490,2'b00};
|
state <= DECODE;
|
next_state(DECODE);
|
end
|
end
|
else if (isExec) begin
|
else if (isExec) begin
|
ir <= exbuf;
|
ir <= exbuf;
|
exbuf <= 64'd0;
|
exbuf <= 64'd0;
|
suppress_pcinc <= 4'h0;
|
suppress_pcinc <= 4'h0;
|
state <= DECODE;
|
next_state(DECODE);
|
end
|
end
|
else if (unCachedInsn) begin
|
else if (unCachedInsn) begin
|
if (bhit) begin
|
if (bhit) begin
|
ir <= ibuf + exbuf;
|
ir <= ibuf + exbuf;
|
exbuf <= 64'd0;
|
exbuf <= 64'd0;
|
state <= DECODE;
|
next_state(DECODE);
|
end
|
end
|
else
|
else begin
|
|
pg2 <= pg2;
|
state <= LOAD_IBUF1;
|
state <= LOAD_IBUF1;
|
end
|
end
|
|
end
|
else begin
|
else begin
|
if (ihit) begin
|
if (ihit) begin
|
ir <= insn + exbuf;
|
ir <= insn + exbuf;
|
exbuf <= 64'd0;
|
exbuf <= 64'd0;
|
state <= DECODE;
|
next_state(DECODE);
|
|
end
|
|
else begin
|
|
pg2 <= pg2;
|
|
next_state(ICACHE1);
|
end
|
end
|
else
|
|
state <= ICACHE1;
|
|
end
|
end
|
end
|
end
|
// During a cache miss all these assignments will repeat. It's not a
|
// During a cache miss all these assignments will repeat. It's not a
|
// problem. The history buffer will be stuffed with the same pc address
|
// problem. The history buffer will be stuffed with the same pc address
|
// for several cycles until the cache load is complete.
|
// for several cycles until the cache load is complete.
|
|
`ifdef DEBUG
|
if (hist_capture) begin
|
if (hist_capture) begin
|
history_buf[history_ndx] <= pc;
|
history_buf[history_ndx] <= pc;
|
history_ndx <= history_ndx+7'd1;
|
history_ndx <= history_ndx+7'd1;
|
end
|
end
|
regfile[Rt] <= res;
|
`endif
|
|
regfile[Rt] <= res[31:0];
|
case(Rt)
|
case(Rt)
|
4'h1: acc <= res;
|
4'h1: acc <= res[31:0];
|
4'h2: x <= res;
|
4'h2: x <= res[31:0];
|
4'h3: y <= res;
|
4'h3: y <= res[31:0];
|
default: ;
|
default: ;
|
endcase
|
endcase
|
case(ir9)
|
case(ir9)
|
`TAS,`TXS: begin isp <= res; gie <= 1'b1; end
|
`TAS,`TXS: begin isp <= res[31:0]; gie <= 1'b1; end
|
`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res;
|
`SUB_SP8,`SUB_SP16,`SUB_SP32: isp <= res[31:0];
|
`TRS:
|
`TRS:
|
begin
|
begin
|
case(ir[15:12])
|
case(ir[15:12])
|
4'h0: begin
|
4'h0: begin
|
$display("res=%h",res);
|
$display("res=%h",res);
|
| Line 136... |
Line 146... |
`ifdef SUPPORT_DCACHE
|
`ifdef SUPPORT_DCACHE
|
dcacheOn <= res[1];
|
dcacheOn <= res[1];
|
write_allocate <= res[2];
|
write_allocate <= res[2];
|
`endif
|
`endif
|
end
|
end
|
4'h5: lfsr <= res;
|
4'h5: lfsr <= res[31:0];
|
4'h7: abs8 <= res;
|
4'h7: abs8 <= res[31:0];
|
4'h8: begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
|
4'h8: begin vbr <= {res[31:9],9'h000}; nmoi <= res[0]; end
|
4'hE: begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end
|
4'hE: begin sp <= res[7:0]; spage[31:8] <= res[31:8]; end
|
4'hF: begin isp <= res; gie <= 1'b1; end
|
4'hF: begin isp <= res[31:0]; gie <= 1'b1; end
|
endcase
|
endcase
|
end
|
end
|
`RR:
|
`RR:
|
case(ir[23:20])
|
case(ir[23:20])
|
`ADD_RR: begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
|
`ADD_RR: begin vf <= resv32; cf <= resc32; nf <= resn32; zf <= resz32; end
|
