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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load.v] - Diff between revs 20 and 21

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Rev 20	Rev 21
Line 47...	Line 47...
`adr_o <= 34'd0;`	`adr_o <= 34'd0;`
`b8 <= dati;`	`b8 <= dati;`
`b <= dat_i;`	`b <= dat_i;`
`state <= em ? BYTE_CALC : CALC;`	`state <= em ? BYTE_CALC : CALC;`
`end`	`end`
	`else if (err_i) begin`
	`cyc_o <= 1'b0;`
	`stb_o <= 1'b0;`
	`sel_o <= 4'h0;`
	`adr_o <= 34'd0;`
	`state <= BUS_ERROR;`
	`end`

`No newline at end of file`	`No newline at end of file`

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