URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_mac.v] - Diff between revs 22 and 23

Rev 22	Rev 23
Line 41...	Line 41...
`WORD_311: // For pla/plx/ply/pop	`WORD_311: // For pla/plx/ply/pop
`begin`	`begin`
`res <= rdat;`	`res <= rdat;`
`state <= IFETCH;`	`state <= IFETCH;`
`end`	`end`
	`WORD_312:
	`begin`
	`b <= rdat;`
	`state <= retstate;`
	`end`
`BYTE_70:	`BYTE_70:
`begin`	`begin`
`b8 <= rdat8;`	`b8 <= rdat8;`
`state <= BYTE_CALC;`	`state <= BYTE_CALC;`
`end`	`end`
Line 189...	Line 194...
`WORD_311: // For pla/plx/ply/pop/ldx/ldy	`WORD_311: // For pla/plx/ply/pop/ldx/ldy
`begin`	`begin`
`res <= dat_i;`	`res <= dat_i;`
`state <= IFETCH;`	`state <= IFETCH;`
`end`	`end`
	`WORD_312:
	`begin`
	`b <= dat_i;`
	`state <= retstate;`
	`end`
`BYTE_70:	`BYTE_70:
`begin`	`begin`
`b8 <= dati;`	`b8 <= dati;`
`state <= BYTE_CALC;`	`state <= BYTE_CALC;`
`end`	`end`
Line 324...	Line 334...
`lock_o <= 1'b0;`	`lock_o <= 1'b0;`
`cyc_o <= 1'b0;`	`cyc_o <= 1'b0;`
`stb_o <= 1'b0;`	`stb_o <= 1'b0;`
`we_o <= 1'b0;`	`we_o <= 1'b0;`
`sel_o <= 4'h0;`	`sel_o <= 4'h0;`
`adr_o <= 34'h0;`
`dat_o <= 32'h0;`	`dat_o <= 32'h0;`
`state <= BUS_ERROR;`	`state <= BUS_ERROR;`
`end`	`end`
`RTS1:`	`RTS1:`
`begin`	`begin`