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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_mac.v] - Diff between revs 32 and 35
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| Rev 32 |
Rev 35 |
| Line 25... |
Line 25... |
if (unCachedData)
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if (unCachedData)
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`endif
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`endif
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begin
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begin
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if (isRMW)
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if (isRMW)
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lock_o <= 1'b1;
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lock_o <= 1'b1;
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cyc_o <= 1'b1;
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wb_read({radr,2'b00});
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stb_o <= 1'b1;
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sel_o <= 4'hF;
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adr_o <= {radr,2'b00};
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state <= LOAD_MAC2;
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state <= LOAD_MAC2;
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end
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end
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`ifdef SUPPORT_DCACHE
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`ifdef SUPPORT_DCACHE
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else if (dhit)
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else if (dhit)
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load_tsk(rdat,rdat8);
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load_tsk(rdat,rdat8);
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| Line 41... |
Line 38... |
state <= DCACHE1;
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state <= DCACHE1;
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end
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end
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`endif
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`endif
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LOAD_MAC2:
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LOAD_MAC2:
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if (ack_i) begin
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if (ack_i) begin
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cyc_o <= 1'b0;
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wb_nack();
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stb_o <= 1'b0;
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sel_o <= 4'h0;
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adr_o <= 34'h0;
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load_tsk(dat_i,dati);
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load_tsk(dat_i,dati);
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end
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end
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`ifdef SUPPORT_BERR
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`ifdef SUPPORT_BERR
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else if (err_i) begin
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else if (err_i) begin
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lock_o <= 1'b0;
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lock_o <= 1'b0;
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cyc_o <= 1'b0;
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wb_nack();
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stb_o <= 1'b0;
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if (em | isOrb)
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we_o <= 1'b0;
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derr_address <= adr_o[31:0];
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sel_o <= 4'h0;
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else
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dat_o <= 32'h0;
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derr_address <= adr_o[33:2];
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intno <= 9'd508;
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state <= BUS_ERROR;
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state <= BUS_ERROR;
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end
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end
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`endif
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`endif
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LOAD_MAC3:
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LOAD_MAC3:
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begin
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begin
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regfile[Rt] <= res;
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regfile[Rt] <= res[31:0];
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case(Rt)
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case(Rt)
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4'h1: acc <= res;
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4'h1: acc <= res[31:0];
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4'h2: x <= res;
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4'h2: x <= res[31:0];
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4'h3: y <= res;
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4'h3: y <= res[31:0];
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default: ;
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default: ;
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endcase
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endcase
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// Rt will be zero by the time the IFETCH stage is entered because of
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// Rt will be zero by the time the IFETCH stage is entered because of
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// the decrement below.
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// the decrement below.
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if (Rt==4'd1)
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if (Rt==4'd1)
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