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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_mac.v] - Diff between revs 35 and 36
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| Rev 35 |
Rev 36 |
| Line 55... |
Line 55... |
state <= BUS_ERROR;
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state <= BUS_ERROR;
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end
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end
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`endif
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`endif
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LOAD_MAC3:
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LOAD_MAC3:
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begin
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begin
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regfile[Rt] <= res[31:0];
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case(Rt)
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4'h1: acc <= res[31:0];
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4'h2: x <= res[31:0];
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4'h3: y <= res[31:0];
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default: ;
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endcase
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// Rt will be zero by the time the IFETCH stage is entered because of
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// Rt will be zero by the time the IFETCH stage is entered because of
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// the decrement below.
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// the decrement below.
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if (Rt==4'd1)
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if (Rt==4'd1)
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state <= IFETCH;
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state <= IFETCH;
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else begin
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else begin
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| Line 87... |
Line 80... |
wadr <= radr + y;
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wadr <= radr + y;
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if (ir9==`ST_IY) begin
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if (ir9==`ST_IY) begin
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store_what <= `STW_A;
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store_what <= `STW_A;
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state <= STORE1;
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state <= STORE1;
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end
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end
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else if (ir9==`LEA_IY) begin
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res <= radr + y;
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next_state(IFETCH);
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end
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else begin
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else begin
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load_what <= `WORD_310;
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load_what <= `WORD_310;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
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isIY <= 1'b0;
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isIY <= 1'b0;
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