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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_mac.v] - Diff between revs 36 and 38
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| Rev 36 |
Rev 38 |
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Line 1... |
// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013, 2014 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@opencores.org
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// \/_// robfinch<remove>@opencores.org
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// ||
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// ||
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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Line 89... |
else begin
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else begin
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load_what <= `WORD_310;
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load_what <= `WORD_310;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
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isIY <= 1'b0;
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isIY <= 1'b0;
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isIY24 <= `FALSE;
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end
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end
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`ifdef SUPPORT_EM8
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`ifdef SUPPORT_EM8
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BYTE_IX5:
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BYTE_IX5:
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begin
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begin
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isI24 <= `FALSE;
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radr <= ia[31:2];
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radr <= ia[31:2];
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radr2LSB <= ia[1:0];
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radr2LSB <= ia[1:0];
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load_what <= `BYTE_70;
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load_what <= m16 ? `HALF_70 : `BYTE_70;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I) begin
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if (ir[7:0]==`STA_IX || ir[7:0]==`STA_I || ir[7:0]==`STA_IL) begin
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wadr <= ia[31:2];
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wadr <= ia[31:2];
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wadr2LSB <= ia[1:0];
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wadr2LSB <= ia[1:0];
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store_what <= `STW_ACC8;
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store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
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state <= STORE1;
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state <= STORE1;
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end
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end
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`ifdef SUPPORT_816
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else if (ir[7:0]==`PEI) begin
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set_sp();
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store_what <= `STW_IA158;
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state <= STORE1;
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end
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`endif
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end
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end
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BYTE_IY5:
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BYTE_IY5:
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begin
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begin
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isIY <= `FALSE;
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isIY <= `FALSE;
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isIY24 <= `FALSE;
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radr <= iapy8[31:2];
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radr <= iapy8[31:2];
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radr2LSB <= iapy8[1:0];
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radr2LSB <= iapy8[1:0];
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$display("IY addr: %h", iapy8);
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$display("IY addr: %h", iapy8);
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if (ir[7:0]==`STA_IY) begin
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if (ir[7:0]==`STA_IY || ir[7:0]==`STA_IYL || ir[7:0]==`STA_DSPIY) begin
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wadr <= iapy8[31:2];
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wadr <= iapy8[31:2];
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wadr2LSB <= iapy8[1:0];
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wadr2LSB <= iapy8[1:0];
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store_what <= `STW_ACC8;
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store_what <= m16 ? `STW_ACC70 : `STW_ACC8;
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state <= STORE1;
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state <= STORE1;
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end
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end
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else begin
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else begin
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load_what <= `BYTE_70;
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load_what <= m16 ? `HALF_70 : `BYTE_70;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
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end
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end
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`endif
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`endif
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No newline at end of file
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No newline at end of file
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