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URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Diff between revs 32 and 35

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Rev 32	Rev 35
Line 40...	Line 40...
`begin`	`begin`
`b <= dat;`	`b <= dat;`
`radr <= y;`	`radr <= y;`
`wadr <= y;`	`wadr <= y;`
store_what <= `STW_B;	store_what <= `STW_B;
`x <= res;`	`x <= res[31:0];`
`acc <= acc - 32'd1;`	`acc <= acc - 32'd1;`
`state <= STORE1;`	`state <= STORE1;`
`end`	`end`
`WORD_313:	`WORD_313:
`begin`	`begin`
`a <= dat;`	`a <= dat;`
`radr <= y;`	`radr <= y;`
load_what <= `WORD_314;	load_what <= `WORD_314;
`x <= res;`	`x <= res[31:0];`
`state <= LOAD_MAC1;`	`state <= LOAD_MAC1;`
`end`	`end`
`WORD_314:	`WORD_314:
`begin`	`begin`
`b <= dat;`	`b <= dat;`
Line 160...	Line 160...
`PC_310: begin	`PC_310: begin
`pc <= dat;`	`pc <= dat;`
load_what <= `NOTHING;	load_what <= `NOTHING;
`if (isRTI) begin`	`if (isRTI) begin`
km <= `FALSE;	km <= `FALSE;
	`ifdef DEBUG
hist_capture <= `TRUE;	hist_capture <= `TRUE;
	`endif
`end`	`end`
`state <= em ? BYTE_IFETCH : IFETCH;`	`state <= em ? BYTE_IFETCH : IFETCH;`
`end`	`end`
`IA_310:	`IA_310:
`begin`	`begin`

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