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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Diff between revs 35 and 36
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| Rev 35 |
Rev 36 |
| Line 31... |
Line 31... |
b8 <= dat8; // for the orb instruction
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b8 <= dat8; // for the orb instruction
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state <= CALC;
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state <= CALC;
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end
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end
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`WORD_311: // For pla/plx/ply/pop/ldx/ldy
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`WORD_311: // For pla/plx/ply/pop/ldx/ldy
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begin
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begin
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if (ir9==`POP)
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Rt <= ir[15:12];
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res <= dat;
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res <= dat;
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state <= isPopa ? LOAD_MAC3 : IFETCH;
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state <= isPopa ? LOAD_MAC3 : IFETCH;
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end
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end
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`WORD_312:
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`WORD_312:
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begin
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begin
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| Line 175... |
Line 177... |
wdat <= a;
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wdat <= a;
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if (isIY)
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if (isIY)
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state <= IY3;
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state <= IY3;
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else if (ir9==`ST_IX)
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else if (ir9==`ST_IX)
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state <= STORE1;
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state <= STORE1;
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else if (ir9==`LEA_IX) begin
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res <= dat;
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next_state(IFETCH);
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end
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else begin
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else begin
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load_what <= `WORD_310;
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load_what <= `WORD_310;
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state <= LOAD_MAC1;
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state <= LOAD_MAC1;
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end
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end
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end
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end
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