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Subversion Repositories rtf65002

[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Diff between revs 36 and 38

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Rev 36	Rev 38
Line 1...	Line 1...
`// ============================================================================`	`// ============================================================================`
`// __`	`// __`
`// \\__/ o\ (C) 2013 Robert Finch, Stratford`	`// \\__/ o\ (C) 2013,2014 Robert Finch, Stratford`
`// \ __ / All rights reserved.`	`// \ __ / All rights reserved.`
`// \/_// robfinch<remove>@opencores.org`	`// \/_// robfinch<remove>@opencores.org`
`// \|\|`	`// \|\|`
`//`	`//`
`// This source file is free software: you can redistribute it and/or modify`	`// This source file is free software: you can redistribute it and/or modify`
Line 43...	Line 43...
`b <= dat;`	`b <= dat;`
`radr <= y;`	`radr <= y;`
`wadr <= y;`	`wadr <= y;`
store_what <= `STW_B;	store_what <= `STW_B;
`x <= res[31:0];`	`x <= res[31:0];`
`acc <= acc - 32'd1;`	`acc <= acc_dec;`
`state <= STORE1;`	`state <= STORE1;`
`end`	`end`
`WORD_313:	`WORD_313:
`begin`	`begin`
`a <= dat;`	`a <= dat;`
Line 72...	Line 72...
`begin`	`begin`
`res8 <= dat8;`	`res8 <= dat8;`
`state <= BYTE_IFETCH;`	`state <= BYTE_IFETCH;`
`end`	`end`
`endif	`endif
	`ifdef SUPPORT_816
	`HALF_70:
	`begin`
	`b16[7:0] <= dat8;`
	load_what <= `HALF_158;
	`if (radr2LSB==2'b11)`
	`radr <= radr+32'd1;`
	`radr2LSB <= radr2LSB + 2'b01;`
	`state <= LOAD_MAC1;`
	`end`
	`HALF_158:
	`begin`
	`b16[15:8] <= dat8;`
	`state <= HALF_CALC;`
	`end`
	`HALF_71:
	`begin`
	`res16[7:0] <= dat8;`
	load_what <= `HALF_159;
	`if (radr2LSB==2'b11)`
	`radr <= radr+32'd1;`
	`radr2LSB <= radr2LSB + 2'b01;`
	`next_state(LOAD_MAC1);`
	`end`
	`HALF_159:
	`begin`
	`res16[15:8] <= dat8;`
	`next_state(BYTE_IFETCH);`
	`end`
	`HALF_71S:
	`begin`
	`res16[7:0] <= dat8;`
	load_what <= `HALF_159S;
	`inc_sp();`
	`next_state(LOAD_MAC1);`
	`end`
	`HALF_159S:
	`begin`
	`res16[15:8] <= dat8;`
	`next_state(BYTE_IFETCH);`
	`end`
	`BYTE_72:
	`begin`
	`wdat[7:0] <= dat8;`
	`radr <= mvndst_address[31:2];`
	`radr2LSB <= mvndst_address[1:0];`
	`wadr <= mvndst_address[31:2];`
	`wadr2LSB <= mvndst_address[1:0];`
	store_what <= `STW_DEF8;
	`acc[15:0] <= acc_dec[15:0];`
	if (ir9==`MVN) begin
	`x[15:0] <= x_inc[15:0];`
	`y[15:0] <= y_inc[15:0];`
	`end`
	`else begin`
	`x[15:0] <= x_dec[15:0];`
	`y[15:0] <= y_dec[15:0];`
	`end`
	`next_state(STORE1);`
	`end`
	`endif
`SR_310: begin	`SR_310: begin
`cf <= dat[0];`	`cf <= dat[0];`
`zf <= dat[1];`	`zf <= dat[1];`
`im <= dat[2];`	`im <= dat[2];`
`df <= dat[3];`	`df <= dat[3];`
`bf <= dat[4];`	`bf <= dat[4];`
	`x_bit <= dat[8];`
	`m_bit <= dat[9];`
	`m816 <= dat[10];`
`tf <= dat[28];`	`tf <= dat[28];`
`em <= dat[29];`	`em <= dat[29];`
`vf <= dat[30];`	`vf <= dat[30];`
`nf <= dat[31];`	`nf <= dat[31];`
`if (isRTI) begin`	`if (isRTI) begin`
	`// If we will be returning to emulation mode and emulating the 816`
	`// then force the upper part of the registers to zero if eigth bit`
	`// registers are selected.`
	`// if (dat[10] & dat[29]) begin`
	`// if (dat[8]) begin`
	`// x[31:8] <= 24'd0;`
	`// y[31:8] <= 24'd0;`
	`// end`
	`// //if (dat[9]) acc[31:8] <= 24'd0;`
	`// end`
`radr <= isp;`	`radr <= isp;`
`isp <= isp_inc;`	`isp <= isp_inc;`
load_what <= `PC_310;	load_what <= `PC_310;
`state <= LOAD_MAC1;`	`state <= LOAD_MAC1;`
`end`	`end`
Line 97...	Line 171...
`SR_70: begin	`SR_70: begin
`cf <= dat8[0];`	`cf <= dat8[0];`
`zf <= dat8[1];`	`zf <= dat8[1];`
`im <= dat8[2];`	`im <= dat8[2];`
`df <= dat8[3];`	`df <= dat8[3];`
	`if (m816) begin`
	`x_bit <= dat8[4];`
	`m_bit <= dat8[5];`
	`if (dat8[4]) begin`
	`x[31:8] <= 24'd0;`
	`y[31:8] <= 24'd0;`
	`end`
	`//if (dat8[5]) acc[31:8] <= 24'd0;`
	`end`
	`else`
`bf <= dat8[4];`	`bf <= dat8[4];`
`vf <= dat8[6];`	`vf <= dat8[6];`
`nf <= dat8[7];`	`nf <= dat8[7];`
`if (isRTI) begin`	`if (isRTI) begin`
load_what <= `PC_70;	load_what <= `PC_70;
`radr <= {spage[31:8],sp_inc[7:2]};`	`inc_sp();`
`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`
`state <= LOAD_MAC1;`	`state <= LOAD_MAC1;`
`end`	`end`
`else // PLP`	`else // PLP`
`state <= BYTE_IFETCH;`	`state <= BYTE_IFETCH;`
`end`	`end`
`PC_70: begin	`PC_70: begin
`pc[7:0] <= dat8;`	`pc[7:0] <= dat8;`
load_what <= `PC_158;	load_what <= `PC_158;
`if (isRTI\|isRTS\|isRTL) begin`	`if (isRTI\|isRTS\|isRTL) begin`
`radr <= {spage[31:8],sp_inc[7:2]};`	`inc_sp();`
`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`
`end`	`end`
`else begin // JMP (abs)`	`else begin // JMP (abs)`
`radr <= radr34p1[33:2];`	`radr <= radr34p1[33:2];`
`radr2LSB <= radr34p1[1:0];`	`radr2LSB <= radr34p1[1:0];`
`end`	`end`
`state <= LOAD_MAC1;`	`state <= LOAD_MAC1;`
`end`	`end`
`PC_158: begin	`PC_158: begin
`pc[15:8] <= dat8;`	`pc[15:8] <= dat8;`
`if (isRTI\|isRTL) begin`	`if ((isRTI&m816)\|isRTL) begin`
load_what <= `PC_2316;	load_what <= `PC_2316;
`radr <= {spage[31:8],sp_inc[7:2]};`	`inc_sp();`
`radr2LSB <= sp_inc[1:0];`
`sp <= sp_inc;`
`state <= LOAD_MAC1;`	`state <= LOAD_MAC1;`
`end`	`end`
`else if (isRTS) // rts instruction`	`else if (isRTS) // rts instruction`
`state <= RTS1;`	`next_state(RTS1);`
`else // jmp (abs)`	`else // jmp (abs)`
`state <= BYTE_IFETCH;`	`next_state(BYTE_IFETCH);`
`end`	`end`
`PC_2316: begin	`PC_2316: begin
`pc[23:16] <= dat8;`	`pc[23:16] <= dat8;`
load_what <= `PC_3124;	`if (isRTL) begin`
`if (isRTI\|isRTL) begin`	load_what <= `NOTHING;
`radr <= {spage[31:8],sp_inc[7:2]};`	`next_state(RTS1);`
`radr2LSB <= sp_inc[1:0];`	`end`
`sp <= sp_inc;`	`else begin`
	load_what <= `NOTHING;
	`next_state(BYTE_IFETCH);`
	// load_what <= `PC_3124;
	`// if (isRTI) begin`
	`// inc_sp();`
	`// end`
	`// state <= LOAD_MAC1;`
`end`	`end`
`state <= LOAD_MAC1;`
`end`	`end`
`PC_3124: begin	`PC_3124: begin
`pc[31:24] <= dat8;`	`pc[31:24] <= dat8;`
load_what <= `NOTHING;	load_what <= `NOTHING;
`if (isRTL)`	`next_state(BYTE_IFETCH);`
`state <= RTS1;`
`else`
`state <= BYTE_IFETCH;`
`end`	`end`
`endif	`endif
`PC_310: begin	`PC_310: begin
`pc <= dat;`	`pc <= dat;`
load_what <= `NOTHING;	load_what <= `NOTHING;
Line 166...	Line 247...
km <= `FALSE;	km <= `FALSE;
`ifdef DEBUG	`ifdef DEBUG
hist_capture <= `TRUE;	hist_capture <= `TRUE;
`endif	`endif
`end`	`end`
`state <= em ? BYTE_IFETCH : IFETCH;`	`next_state(em ? BYTE_IFETCH : IFETCH);`
	`// else // indirect jumps`
	`// next_state(IFETCH);`
`end`	`end`
`IA_310:	`IA_310:
`begin`	`begin`
`radr <= dat;`	`radr <= dat;`
`wadr <= dat;`	`wadr <= dat;`
Line 198...	Line 281...
`state <= LOAD_MAC1;`	`state <= LOAD_MAC1;`
`end`	`end`
`IA_158:	`IA_158:
`begin`	`begin`
`ia[15:8] <= dat8;`	`ia[15:8] <= dat8;`
`ia[31:16] <= abs8[31:16];`	`ia[31:16] <= {abs8[31:24],dbr};`
	`if (isIY24\|isI24) begin`
	`radr <= radr34p1[33:2];`
	`radr2LSB <= radr34p1[1:0];`
	load_what <= `IA_2316;
	`state <= LOAD_MAC1;`
	`end`
	`else`
`state <= isIY ? BYTE_IY5 : BYTE_IX5;`	`state <= isIY ? BYTE_IY5 : BYTE_IX5;`
`end`	`end`
	`IA_2316:
	`begin`
	`ia[23:16] <= dat8;`
	`ia[31:24] <= abs8[31:24];`
	`state <= isIY24 ? BYTE_IY5 : BYTE_IX5;`
	`end`
`endif	`endif
`endcase`	`endcase`
`end`	`end`
`endtask`	`endtask`

`No newline at end of file`	`No newline at end of file`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [load_tsk.v] - Diff between revs 36 and 38