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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [mult_div.v] - Diff between revs 32 and 35

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Rev 32	Rev 35
Line 25...	Line 25...
`//`	`//`
`include "rtf65002_defines.v"	`include "rtf65002_defines.v"

`module mult_div(rst, clk, ld, op, fn, a, b, p, q, r, done);`	`module mult_div(rst, clk, ld, op, fn, a, b, p, q, r, done);`
`parameter IDLE=3'd0;`	`parameter IDLE=3'd0;`
`parameter MULT=3'd1;`	`parameter MULT1=3'd1;`
`parameter FIX_SIGN=3'd2;`	`parameter MULT2=3'd2;`
`parameter DIV=3'd3;`	`parameter MULT3=3'd3;`
	`parameter FIX_SIGN=3'd4;`
	`parameter DIV=3'd5;`
`input rst;`	`input rst;`
`input clk;`	`input clk;`
`input ld;`	`input ld;`
`input [8:0] op;`	`input [8:0] op;`
`input [3:0] fn;`	`input [3:0] fn;`
Line 48...	Line 50...
`reg [2:0] state;`	`reg [2:0] state;`

`assign done = state==IDLE;`	`assign done = state==IDLE;`
`wire [31:0] diff = r - bb;`	`wire [31:0] diff = r - bb;`
`wire [31:0] pa = a[31] ? -a : a;`	`wire [31:0] pa = a[31] ? -a : a;`
	`wire [63:0] p1 = aa * bb;`
`reg [5:0] cnt;`	`reg [5:0] cnt;`

`always @(posedge clk)`	`always @(posedge clk)`
`if (rst)`	`if (rst)`
`state <= IDLE;`	`state <= IDLE;`
Line 64...	Line 67...
`MUL_IMM8,`MUL_IMM16,`MUL_IMM32:	`MUL_IMM8,`MUL_IMM16,`MUL_IMM32:
`begin`	`begin`
`aa <= a;`	`aa <= a;`
`bb <= b;`	`bb <= b;`
`res_sgn <= 1'b0;`	`res_sgn <= 1'b0;`
`state <= MULT;`	`state <= MULT1;`
`end`	`end`
`ifdef SUPPORT_DIVMOD	`ifdef SUPPORT_DIVMOD
`DIV_IMM8,`DIV_IMM16,`DIV_IMM32,	`DIV_IMM8,`DIV_IMM16,`DIV_IMM32,
`MOD_IMM8,`MOD_IMM16,`MOD_IMM32:	`MOD_IMM8,`MOD_IMM16,`MOD_IMM32:
`begin`	`begin`
Line 85...	Line 88...
`MUL_RR:	`MUL_RR:
`begin`	`begin`
`aa <= a;`	`aa <= a;`
`bb <= b;`	`bb <= b;`
`res_sgn <= 1'b0;`	`res_sgn <= 1'b0;`
`state <= MULT;`	`state <= MULT1;`
`end`	`end`
`MULS_RR:	`MULS_RR:
`begin`	`begin`
`aa <= a[31] ? -a : a;`	`aa <= a[31] ? -a : a;`
`bb <= b[31] ? -b : b;`	`bb <= b[31] ? -b : b;`
`res_sgn <= a[31] ^ b[31];`	`res_sgn <= a[31] ^ b[31];`
`state <= MULT;`	`state <= MULT1;`
`end`	`end`
`ifdef SUPPORT_DIVMOD	`ifdef SUPPORT_DIVMOD
`DIV_RR,`MOD_RR:	`DIV_RR,`MOD_RR:
`begin`	`begin`
`aa <= a;`	`aa <= a;`
Line 119...	Line 122...
`default:`	`default:`
`state <= IDLE;`	`state <= IDLE;`
`endcase`	`endcase`
`endcase`	`endcase`
`end`	`end`
`MULT:`	`// Three waut states for the multiply to take effect. These are needed at`
`begin`	`// higher clock frequencies. The multipler is a multi-cycle path that`
	`// requires a timing constraint.`
	`MULT1: state <= MULT2;`
	`MULT2: state <= MULT3;`
	`MULT3: begin`
	`p <= p1;`
`state <= res_sgn ? FIX_SIGN : IDLE;`	`state <= res_sgn ? FIX_SIGN : IDLE;`
`p <= aa * bb;`
`end`	`end`

`ifdef SUPPORT_DIVMOD	`ifdef SUPPORT_DIVMOD
`DIV:`	`DIV:`
`begin`	`begin`
`q <= {q[30:0],~diff[31]};`	`q <= {q[30:0],~diff[31]};`
`if (cnt==6'd0) begin`	`if (cnt==6'd0) begin`

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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [mult_div.v] - Diff between revs 32 and 35