| Line 51... |
Line 51... |
input [31:0] vbr;
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input [31:0] vbr;
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input nmoi;
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input nmoi;
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input [31:0] derr_address;
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input [31:0] derr_address;
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input [31:0] history_buf;
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input [31:0] history_buf;
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input [31:0] spage;
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input [31:0] spage;
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input [7:0] sp;
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input [15:0] sp;
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input df;
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input df;
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input cf;
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input cf;
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output reg [32:0] res;
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output reg [32:0] res;
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`ifdef SUPPORT_SHIFT
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`ifdef SUPPORT_SHIFT
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| Line 101... |
Line 101... |
4'h8: res <= {vbr[31:1],nmoi};
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4'h8: res <= {vbr[31:1],nmoi};
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4'h9: res <= derr_address;
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4'h9: res <= derr_address;
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`ifdef DEBUG
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`ifdef DEBUG
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4'hA: res <= history_buf;
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4'hA: res <= history_buf;
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`endif
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`endif
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4'hE: res <= {spage[31:8],sp};
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4'hE: res <= {spage[31:16],sp};
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4'hF: res <= isp;
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4'hF: res <= isp;
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default: res <= 33'd0;
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default: res <= 33'd0;
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endcase
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endcase
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end
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end
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`ASL_ACC: res <= {acc,1'b0};
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`ASL_ACC: res <= {acc,1'b0};
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| Line 134... |
Line 134... |
`LSR_RR: res <= {rfoa[0],1'b0,rfoa[31:1]};
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`LSR_RR: res <= {rfoa[0],1'b0,rfoa[31:1]};
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`ROR_RR: res <= {rfoa[0],cf,rfoa[31:1]};
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`ROR_RR: res <= {rfoa[0],cf,rfoa[31:1]};
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`DEC_RR: res <= rfoa - 32'd1;
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`DEC_RR: res <= rfoa - 32'd1;
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`INC_RR: res <= rfoa + 32'd1;
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`INC_RR: res <= rfoa + 32'd1;
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|
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`ADD_R: res <= rfoa + rfob + {31'b0,df&cf};
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`SUB_R: res <= rfoa - rfob - {31'b0,df&~cf&|ir[15:12]};
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`AND_R: res <= rfoa & rfob;
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`OR_R: res <= rfoa | rfob;
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`EOR_R: res <= rfoa ^ rfob;
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|
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`ADD_IMM4: res <= rfoa + {{28{ir[15]}},ir[15:12]} + {31'b0,df&cf};
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`SUB_IMM4: res <= rfoa - {{28{ir[15]}},ir[15:12]} - {31'b0,df&~cf&|ir[11:8]};
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`OR_IMM4: res <= rfoa | {{28{ir[15]}},ir[15:12]};
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`AND_IMM4: res <= rfoa & {{28{ir[15]}},ir[15:12]};
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`EOR_IMM4: res <= rfoa ^ {{28{ir[15]}},ir[15:12]};
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|
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`ADD_IMM8: res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf};
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`ADD_IMM8: res <= rfoa + {{24{ir[23]}},ir[23:16]} + {31'b0,df&cf};
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`SUB_IMM8: res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]};
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`SUB_IMM8: res <= rfoa - {{24{ir[23]}},ir[23:16]} - {31'b0,df&~cf&|ir[15:12]};
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`MUL_IMM8: res <= 33'd0;
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`MUL_IMM8: res <= 33'd0;
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`ifdef SUPPORT_DIVMOD
|
`ifdef SUPPORT_DIVMOD
|
`DIV_IMM8: res <= 33'd0;
|
`DIV_IMM8: res <= 33'd0;
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| Line 185... |
Line 197... |
|
|
`CPX_IMM32: res <= x - ir[39:8];
|
`CPX_IMM32: res <= x - ir[39:8];
|
`CPY_IMM32: res <= y - ir[39:8];
|
`CPY_IMM32: res <= y - ir[39:8];
|
// The following results are available for CALC only after the DECODE/LOAD_MAC
|
// The following results are available for CALC only after the DECODE/LOAD_MAC
|
// stage as the 'a' and 'b' side registers need to be loaded.
|
// stage as the 'a' and 'b' side registers need to be loaded.
|
`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND: res <= a + b + {31'b0,df&cf};
|
`ADD_ZPX,`ADD_IX,`ADD_IY,`ADD_ABS,`ADD_ABSX,`ADD_RIND,`ADD_DSP: res <= a + b + {31'b0,df&cf};
|
`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND: res <= a - b - {31'b0,df&~cf&|Rt}; // Also CMP
|
`SUB_ZPX,`SUB_IX,`SUB_IY,`SUB_ABS,`SUB_ABSX,`SUB_RIND,`SUB_DSP: res <= a - b - {31'b0,df&~cf&|Rt}; // Also CMP
|
`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND: res <= a & b; // Also BIT
|
`AND_ZPX,`AND_IX,`AND_IY,`AND_ABS,`AND_ABSX,`AND_RIND,`AND_DSP: res <= a & b; // Also BIT
|
`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND: res <= a | b; // Also LD
|
`OR_ZPX,`OR_IX,`OR_IY,`OR_ABS,`OR_ABSX,`OR_RIND,`OR_DSP: res <= a | b; // Also LD
|
`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND: res <= a ^ b;
|
`EOR_ZPX,`EOR_IX,`EOR_IY,`EOR_ABS,`EOR_ABSX,`EOR_RIND,`EOR_DSP: res <= a ^ b;
|
`LDX_ZPY,`LDX_ABS,`LDX_ABSY: res <= b;
|
`LDX_ZPY,`LDX_ABS,`LDX_ABSY: res <= b;
|
`LDY_ZPX,`LDY_ABS,`LDY_ABSX: res <= b;
|
`LDY_ZPX,`LDY_ABS,`LDY_ABSX: res <= b;
|
`CPX_ZPX,`CPX_ABS: res <= x - b;
|
`CPX_ZPX,`CPX_ABS: res <= x - b;
|
`CPY_ZPX,`CPY_ABS: res <= y - b;
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`CPY_ZPX,`CPY_ABS: res <= y - b;
|
`ifdef SUPPORT_SHIFT
|
`ifdef SUPPORT_SHIFT
|
| Line 211... |
Line 223... |
`BMC_ZPX,`BMC_ABS,`BMC_ABSX: res <= b & (~(32'b1 << acc[4:0]));
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`BMC_ZPX,`BMC_ABS,`BMC_ABSX: res <= b & (~(32'b1 << acc[4:0]));
|
`BMF_ZPX,`BMF_ABS,`BMF_ABSX: res <= b ^ (32'b1 << acc[4:0]);
|
`BMF_ZPX,`BMF_ABS,`BMF_ABSX: res <= b ^ (32'b1 << acc[4:0]);
|
`BMT_ZPX,`BMT_ABS,`BMT_ABSX: res <= b & (32'b1 << acc[4:0]);
|
`BMT_ZPX,`BMT_ABS,`BMT_ABSX: res <= b & (32'b1 << acc[4:0]);
|
`TRB_ZPX,`TRB_ABS: res <= ~a & b;
|
`TRB_ZPX,`TRB_ABS: res <= ~a & b;
|
`TSB_ZPX,`TSB_ABS: res <= a | b;
|
`TSB_ZPX,`TSB_ABS: res <= a | b;
|
|
`SPL_ABS,`SPL_ABSX: res <= b;
|
default: res <= 33'd0;
|
default: res <= 33'd0;
|
endcase
|
endcase
|
endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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