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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_alu.v] - Diff between revs 35 and 36
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| Rev 35 |
Rev 36 |
| Line 209... |
Line 209... |
`ORB_ZPX,`ORB_ABS,`ORB_ABSX: res <= a | {24'h0,b8};
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`ORB_ZPX,`ORB_ABS,`ORB_ABSX: res <= a | {24'h0,b8};
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`BMS_ZPX,`BMS_ABS,`BMS_ABSX: res <= b | (32'b1 << acc[4:0]);
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`BMS_ZPX,`BMS_ABS,`BMS_ABSX: res <= b | (32'b1 << acc[4:0]);
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`BMC_ZPX,`BMC_ABS,`BMC_ABSX: res <= b & (~(32'b1 << acc[4:0]));
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`BMC_ZPX,`BMC_ABS,`BMC_ABSX: res <= b & (~(32'b1 << acc[4:0]));
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`BMF_ZPX,`BMF_ABS,`BMF_ABSX: res <= b ^ (32'b1 << acc[4:0]);
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`BMF_ZPX,`BMF_ABS,`BMF_ABSX: res <= b ^ (32'b1 << acc[4:0]);
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`BMT_ZPX,`BMT_ABS,`BMT_ABSX: res <= b & (32'b1 << acc[4:0]);
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`BMT_ZPX,`BMT_ABS,`BMT_ABSX: res <= b & (32'b1 << acc[4:0]);
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`TRB_ZPX,`TRB_ABS: res <= ~a & b;
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`TSB_ZPX,`TSB_ABS: res <= a | b;
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default: res <= 33'd0;
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default: res <= 33'd0;
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endcase
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endcase
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endmodule
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endmodule
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