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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_pcinc.v] - Diff between revs 32 and 35

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Rev 32 Rev 35
Line 26... Line 26...
module rtf65002_pcinc(opcode,suppress_pcinc,inc);
module rtf65002_pcinc(opcode,suppress_pcinc,inc);
input [8:0] opcode;
input [8:0] opcode;
input [3:0] suppress_pcinc;
input [3:0] suppress_pcinc;
output reg [3:0] inc;
output reg [3:0] inc;
 
 
always @(opcode)
always @(opcode,suppress_pcinc)
if (suppress_pcinc==4'hF)
if (suppress_pcinc==4'hF)
        case(opcode)
        case(opcode)
        `BRK:   inc <= 4'd0;
        `BRK:   inc <= 4'd0;
        `INT0,`INT1: inc <= 4'd0;
        `INT0,`INT1: inc <= 4'd0;
        `BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA,`BGT,`BLE,`BGE,`BLT,`BHI,`BLS:     inc <= 4'd2;
        `BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA,`BGT,`BLE,`BGE,`BLT,`BHI,`BLS:     inc <= 4'd2;

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