| Line 38... |
Line 38... |
`EXEC,`ATNI: inc <= 4'd2;
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`EXEC,`ATNI: inc <= 4'd2;
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`CLC,`SEC,`CLD,`SED,`CLV,`CLI,`SEI: inc <= 4'd1;
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`CLC,`SEC,`CLD,`SED,`CLV,`CLI,`SEI: inc <= 4'd1;
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`TAS,`TSA,`TAY,`TYA,`TAX,`TXA,`TSX,`TXS,`TYX,`TXY: inc <= 4'd1;
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`TAS,`TSA,`TAY,`TYA,`TAX,`TXA,`TSX,`TXS,`TYX,`TXY: inc <= 4'd1;
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`TRS,`TSR: inc <= 4'd2;
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`TRS,`TSR: inc <= 4'd2;
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`INY,`DEY,`INX,`DEX,`INA,`DEA: inc <= 4'd1;
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`INY,`DEY,`INX,`DEX,`INA,`DEA: inc <= 4'd1;
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`EMM: inc <= 4'd1;
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`XCE: inc <= 4'd1;
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`STP,`WAI: inc <= 4'd1;
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`STP,`WAI: inc <= 4'd1;
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`JMP,`JML,`JMP_IND,`JMP_INDX,`JMP_RIND,
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`JMP,`JML,`JMP_IND,`JMP_INDX,`JMP_RIND,
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`JSR,`JSR_RIND,`JSL,`BSR,`JSR_INDX,`RTS,`RTL,`RTI: inc <= 4'd0;
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`JSR,`JSR_RIND,`JSL,`BSR,`JSR_INDX,`RTS,`RTL,`RTI: inc <= 4'd0;
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`JML,`JSL,`JMP_IND,`JMP_INDX,`JSR_INDX: inc <= 4'd5;
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`JML,`JSL,`JMP_IND,`JMP_INDX,`JSR_INDX: inc <= 4'd5;
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`JMP_RIND,`JSR_RIND: inc <= 4'd2;
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`JMP_RIND,`JSR_RIND: inc <= 4'd2;
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`NOP: inc <= 4'd1;
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`NOP: inc <= 4'd1;
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`BSR: inc <= 4'd3;
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`BSR: inc <= 4'd3;
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`RR: inc <= 4'd3;
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`RR: inc <= 4'd3;
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`LD_RR: inc <= 4'd2;
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`LD_RR: inc <= 4'd2;
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`ADD_IMM4,`SUB_IMM4,`AND_IMM4,`OR_IMM4,`EOR_IMM4,
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`ADD_R,`SUB_R,`AND_R,`OR_R,`EOR_R: inc <= 4'd2;
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`ADD_IMM8,`SUB_IMM8,`AND_IMM8,`OR_IMM8,`EOR_IMM8,`ASL_IMM8,`LSR_IMM8: inc <= 4'd3;
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`ADD_IMM8,`SUB_IMM8,`AND_IMM8,`OR_IMM8,`EOR_IMM8,`ASL_IMM8,`LSR_IMM8: inc <= 4'd3;
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`MUL_IMM8,`DIV_IMM8,`MOD_IMM8: inc <= 4'd3;
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`MUL_IMM8,`DIV_IMM8,`MOD_IMM8: inc <= 4'd3;
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`LDX_IMM8,`LDA_IMM8,`CMP_IMM8,`SUB_SP8: inc <= 4'd2;
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`LDX_IMM8,`LDA_IMM8,`CMP_IMM8,`SUB_SP8: inc <= 4'd2;
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`ADD_IMM16,`SUB_IMM16,`AND_IMM16,`OR_IMM16,`EOR_IMM16: inc <= 4'd4;
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`ADD_IMM16,`SUB_IMM16,`AND_IMM16,`OR_IMM16,`EOR_IMM16: inc <= 4'd4;
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`MUL_IMM16,`DIV_IMM16,`MOD_IMM16: inc <= 4'd4;
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`MUL_IMM16,`DIV_IMM16,`MOD_IMM16: inc <= 4'd4;
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| Line 80... |
Line 82... |
`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS,
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`BMS_ABS,`BMC_ABS,`BMF_ABS,`BMT_ABS,
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`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`CPX_ABS,`CPY_ABS: inc <= 4'd5;
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`ASL_ABS,`ROL_ABS,`LSR_ABS,`ROR_ABS,`INC_ABS,`DEC_ABS,`CPX_ABS,`CPY_ABS: inc <= 4'd5;
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`ORB_ABS,`LDX_ABSY,`LDY_ABSX,`ST_ABS,`STB_ABS,
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`ORB_ABS,`LDX_ABSY,`LDY_ABSX,`ST_ABS,`STB_ABS,
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`ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS,
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`ADD_ABS,`SUB_ABS,`OR_ABS,`AND_ABS,`EOR_ABS,
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`BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX,
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`BMS_ABSX,`BMC_ABSX,`BMF_ABSX,`BMT_ABSX,
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`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX: inc <= 4'd6;
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`ASL_ABSX,`ROL_ABSX,`LSR_ABSX,`ROR_ABSX,`INC_ABSX,`DEC_ABSX,`SPL_ABSX: inc <= 4'd6;
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`ORB_ABSX,`ST_ABSX,`STB_ABSX,
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`ORB_ABSX,`ST_ABSX,`STB_ABSX,
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`ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX: inc <= 4'd7;
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`ADD_ABSX,`SUB_ABSX,`OR_ABSX,`AND_ABSX,`EOR_ABSX: inc <= 4'd7;
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`PHP,`PHA,`PHX,`PHY,`PLP,`PLA,`PLX,`PLY: inc <= 4'd1;
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`PHP,`PHA,`PHX,`PHY,`PLP,`PLA,`PLX,`PLY: inc <= 4'd1;
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`PUSH,`POP: inc <= 4'd2;
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`PUSH,`POP: inc <= 4'd2;
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`MVN,`MVP,`STS: inc <= 4'd0;
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`MVN,`MVP,`STS: inc <= 4'd1;
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`PG2: inc <= 4'd1;
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`PG2: inc <= 4'd1;
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`TON,`TOFF: inc <= 4'd1;
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`TON,`TOFF: inc <= 4'd1;
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`PUSHA,`POPA: inc <= 4'd1;
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`PUSHA,`POPA: inc <= 4'd1;
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`SPL_ABS: inc <= 4'd5;
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default: inc <= 4'd0; // unimplemented instruction
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default: inc <= 4'd0; // unimplemented instruction
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endcase
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endcase
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else
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else
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inc <= 4'd0;
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inc <= 4'd0;
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endmodule
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endmodule
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