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[/] [rtf65002/] [trunk/] [rtl/] [verilog/] [rtf65002_pcinc8.v] - Diff between revs 32 and 35
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module rtf65002_pcinc8(opcode,suppress_pcinc,inc);
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module rtf65002_pcinc8(opcode,suppress_pcinc,inc);
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input [7:0] opcode;
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input [7:0] opcode;
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input [3:0] suppress_pcinc;
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input [3:0] suppress_pcinc;
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output reg [3:0] inc;
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output reg [3:0] inc;
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always @(opcode)
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always @(opcode,suppress_pcinc)
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if (suppress_pcinc==4'hF)
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if (suppress_pcinc==4'hF)
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case(opcode)
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case(opcode)
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`BRK: inc <= 4'd0;
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`BRK: inc <= 4'd0;
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`BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA: inc <= 4'd2;
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`BPL,`BMI,`BCS,`BCC,`BVS,`BVC,`BEQ,`BNE,`BRA: inc <= 4'd2;
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`BRL: inc <= 4'd3;
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`BRL: inc <= 4'd3;
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